Initial commit for the firmware. Used the 20090306_ela version as baseline.

[proxmark3-svn] / fpga / sim.tcl

diff --git a/fpga/sim.tcl b/fpga/sim.tcl
new file mode 100644 (file)
index 0000000..477acd1
--- /dev/null
+++ b/fpga/sim.tcl
@@ -0,0 +1,27 @@
+#------------------------------------------------------------------------------\r
+# Run the simulation testbench in ModelSim: recompile both Verilog source\r
+# files, then start the simulation, add a lot of signals to the waveform\r
+# viewer, and run. I should (TODO) fix the absolute paths at some point.\r
+#\r
+# Jonathan Westhues, Mar 2006\r
+#------------------------------------------------------------------------------\r
+\r
+vlog -work work -O0 C:/depot/proximity/mark3/fpga/fpga.v\r
+vlog -work work -O0 C:/depot/proximity/mark3/fpga/fpga_tb.v\r
+\r
+vsim work.fpga_tb\r
+\r
+add wave sim:/fpga_tb/adc_clk\r
+add wave sim:/fpga_tb/adc_d\r
+add wave sim:/fpga_tb/pwr_lo\r
+add wave sim:/fpga_tb/ssp_clk\r
+add wave sim:/fpga_tb/ssp_frame\r
+add wave sim:/fpga_tb/ssp_din\r
+add wave sim:/fpga_tb/ssp_dout\r
+\r
+add wave sim:/fpga_tb/dut/clk_lo\r
+add wave sim:/fpga_tb/dut/pck_divider\r
+add wave sim:/fpga_tb/dut/carrier_divider_lo\r
+add wave sim:/fpga_tb/dut/conf_word\r
+\r
+run 30000\r