--- /dev/null
+`include "lo_read.v"\r
+\r
+/*\r
+ pck0 - input main 24Mhz clock (PLL / 4)\r
+ [7:0] adc_d - input data from A/D converter\r
+ lo_is_125khz - input freq selector (1=125Khz, 0=136Khz)\r
+\r
+ pwr_lo - output to coil drivers (ssp_clk / 8)\r
+ adc_clk - output A/D clock signal\r
+ ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)\r
+ ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)\r
+ ssp_clk - output SSP clock signal 1Mhz/1.09Mhz (pck0 / 2*(11+lo_is_125khz) )\r
+\r
+ ck_1356meg - input unused\r
+ ck_1356megb - input unused\r
+ ssp_dout - input unused\r
+ cross_hi - input unused\r
+ cross_lo - input unused\r
+\r
+ pwr_hi - output unused, tied low\r
+ pwr_oe1 - output unused, undefined\r
+ pwr_oe2 - output unused, undefined\r
+ pwr_oe3 - output unused, undefined\r
+ pwr_oe4 - output unused, undefined\r
+ dbg - output alias for adc_clk\r
+*/\r
+\r
+module testbed_lo_read;\r
+ reg pck0;\r
+ reg [7:0] adc_d;\r
+ reg lo_is_125khz;\r
+\r
+ wire pwr_lo;\r
+ wire adc_clk;\r
+ wire ck_1356meg;\r
+ wire ck_1356megb;\r
+ wire ssp_frame;\r
+ wire ssp_din;\r
+ wire ssp_clk;\r
+ wire ssp_dout;\r
+ wire pwr_hi;\r
+ wire pwr_oe1;\r
+ wire pwr_oe2;\r
+ wire pwr_oe3;\r
+ wire pwr_oe4;\r
+ wire cross_lo;\r
+ wire cross_hi;\r
+ wire dbg;\r
+\r
+ lo_read #(5,200) dut(\r
+ .pck0(pck0),\r
+ .ck_1356meg(ck_1356meg),\r
+ .ck_1356megb(ck_1356megb),\r
+ .pwr_lo(pwr_lo),\r
+ .pwr_hi(pwr_hi),\r
+ .pwr_oe1(pwr_oe1),\r
+ .pwr_oe2(pwr_oe2),\r
+ .pwr_oe3(pwr_oe3),\r
+ .pwr_oe4(pwr_oe4),\r
+ .adc_d(adc_d),\r
+ .adc_clk(adc_clk),\r
+ .ssp_frame(ssp_frame),\r
+ .ssp_din(ssp_din),\r
+ .ssp_dout(ssp_dout),\r
+ .ssp_clk(ssp_clk),\r
+ .cross_hi(cross_hi),\r
+ .cross_lo(cross_lo),\r
+ .dbg(dbg),\r
+ .lo_is_125khz(lo_is_125khz)\r
+ );\r
+\r
+ integer idx, i;\r
+\r
+ // main clock\r
+ always #5 pck0 = !pck0;\r
+\r
+ //new A/D value available from ADC on positive edge\r
+ task crank_dut;\r
+ begin\r
+ @(posedge adc_clk) ;\r
+ adc_d = $random;\r
+ end\r
+ endtask\r
+\r
+ initial begin\r
+\r
+ // init inputs\r
+ pck0 = 0;\r
+ adc_d = 0;\r
+\r
+ // simulate 4 A/D cycles at 134Khz\r
+ lo_is_125khz=0;\r
+ for (i = 0 ; i < 4 ; i = i + 1) begin\r
+ crank_dut;\r
+ end\r
+\r
+ // simulate 4 A/D cycles at 125Khz\r
+ lo_is_125khz=1;\r
+ for (i = 0 ; i < 4 ; i = i + 1) begin\r
+ crank_dut;\r
+ end\r
+ $finish;\r
+ end\r
+ \r
+endmodule // main\r