Initial commit for the firmware. Used the 20090306_ela version as baseline.

[proxmark3-svn] / fpga / testbed_lo_simulate.v

diff --git a/fpga/testbed_lo_simulate.v b/fpga/testbed_lo_simulate.v
new file mode 100644 (file)
index 0000000..d30f822
--- /dev/null
+++ b/fpga/testbed_lo_simulate.v
@@ -0,0 +1,101 @@
+`include "lo_simulate.v"\r
+\r
+/*\r
+       pck0                    - input main 24Mhz clock (PLL / 4)\r
+       [7:0] adc_d             - input data from A/D converter\r
+\r
+\r
+       pwr_lo                  - output to coil drivers (ssp_clk / 8)\r
+       adc_clk                 - output A/D clock signal\r
+       ssp_frame               - output SSS frame indicator (goes high while the 8 bits are shifted)\r
+       ssp_din                 - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)\r
+       ssp_clk                 - output SSP clock signal\r
+\r
+       ck_1356meg              - input unused\r
+       ck_1356megb             - input unused\r
+       ssp_dout                - input unused\r
+       cross_hi                - input unused\r
+       cross_lo                - input unused\r
+\r
+       pwr_hi                  - output unused, tied low\r
+       pwr_oe1                 - output unused, undefined\r
+       pwr_oe2                 - output unused, undefined\r
+       pwr_oe3                 - output unused, undefined\r
+       pwr_oe4                 - output unused, undefined\r
+       dbg                             - output alias for adc_clk\r
+*/\r
+\r
+module testbed_lo_simulate;\r
+       reg  pck0;\r
+       reg  [7:0] adc_d;\r
+\r
+\r
+       wire pwr_lo;\r
+       wire adc_clk;\r
+       wire ck_1356meg;\r
+       wire ck_1356megb;\r
+       wire ssp_frame;\r
+       wire ssp_din;\r
+       wire ssp_clk;\r
+       reg  ssp_dout;\r
+       wire pwr_hi;\r
+       wire pwr_oe1;\r
+       wire pwr_oe2;\r
+       wire pwr_oe3;\r
+       wire pwr_oe4;\r
+       reg  cross_lo;\r
+       wire cross_hi;\r
+       wire dbg;\r
+\r
+       lo_simulate #(5,200) dut(\r
+       .pck0(pck0),\r
+       .ck_1356meg(ck_1356meg),\r
+       .ck_1356megb(ck_1356megb),\r
+       .pwr_lo(pwr_lo),\r
+       .pwr_hi(pwr_hi),\r
+       .pwr_oe1(pwr_oe1),\r
+       .pwr_oe2(pwr_oe2),\r
+       .pwr_oe3(pwr_oe3),\r
+       .pwr_oe4(pwr_oe4),\r
+       .adc_d(adc_d),\r
+       .adc_clk(adc_clk),\r
+       .ssp_frame(ssp_frame),\r
+       .ssp_din(ssp_din),\r
+       .ssp_dout(ssp_dout),\r
+       .ssp_clk(ssp_clk),\r
+       .cross_hi(cross_hi),\r
+       .cross_lo(cross_lo),\r
+       .dbg(dbg)\r
+       );\r
+\r
+\r
+       integer i, counter=0;\r
+\r
+       // main clock\r
+       always #5 pck0 = !pck0;\r
+\r
+       //cross_lo is not really synced to pck0 but it's roughly pck0/192 (24Mhz/192=125Khz)\r
+       task crank_dut;\r
+       begin\r
+               @(posedge pck0) ;\r
+               counter = counter + 1;\r
+               if (counter == 192) begin\r
+                       counter = 0;\r
+                       ssp_dout = $random;\r
+                       cross_lo = 1;\r
+               end else begin\r
+                       cross_lo = 0;\r
+               end\r
+                       \r
+       end\r
+       endtask\r
+\r
+       initial begin\r
+               pck0 = 0;\r
+               for (i = 0 ;  i < 4096 ;  i = i + 1) begin\r
+                       crank_dut;\r
+               end\r
+               $finish;\r
+       end\r
+\r
+endmodule // main\r