--- /dev/null
+//-----------------------------------------------------------------------------\r
+// Incomplete register definitions for the AT91SAM7S128 chip.\r
+// Jonathan Westhues, Jul 2005\r
+//-----------------------------------------------------------------------------\r
+\r
+#ifndef __AT91SAM7S128_H\r
+#define __AT91SAM7S128_H\r
+\r
+#define REG(x) (*(volatile unsigned long *)(x))\r
+\r
+//-------------\r
+// Peripheral IDs\r
+\r
+#define PERIPH_AIC_FIQ 0\r
+#define PERIPH_SYSIRQ 1\r
+#define PERIPH_PIOA 2\r
+#define PERIPH_ADC 4\r
+#define PERIPH_SPI 5\r
+#define PERIPH_US0 6\r
+#define PERIPH_US1 7\r
+#define PERIPH_SSC 8\r
+#define PERIPH_TWI 9\r
+#define PERIPH_PWMC 10\r
+#define PERIPH_UDP 11\r
+#define PERIPH_TC0 12\r
+#define PERIPH_TC1 13\r
+#define PERIPH_TC2 14\r
+#define PERIPH_AIC_IRQ0 30\r
+#define PERIPH_AIC_IRQ1 31\r
+\r
+//-------------\r
+// Reset Controller\r
+\r
+#define RSTC_BASE (0xfffffd00)\r
+\r
+#define RSTC_CONTROL REG(RSTC_BASE+0x00)\r
+\r
+#define RST_CONTROL_KEY (0xa5<<24)\r
+#define RST_CONTROL_PROCESSOR_RESET (1<<0)\r
+\r
+//-------------\r
+// PWM Controller\r
+\r
+#define PWM_BASE (0xfffcc000)\r
+\r
+#define PWM_MODE REG(PWM_BASE+0x00)\r
+#define PWM_ENABLE REG(PWM_BASE+0x04)\r
+#define PWM_DISABLE REG(PWM_BASE+0x08)\r
+#define PWM_STATUS REG(PWM_BASE+0x0c)\r
+#define PWM_INTERRUPT_ENABLE REG(PWM_BASE+0x10)\r
+#define PWM_INTERRUPT_DISABLE REG(PWM_BASE+0x14)\r
+#define PWM_INTERRUPT_MASK REG(PWM_BASE+0x18)\r
+#define PWM_INTERRUPT_STATUS REG(PWM_BASE+0x1c)\r
+#define PWM_CH_MODE(x) REG(PWM_BASE+0x200+((x)*0x20))\r
+#define PWM_CH_DUTY_CYCLE(x) REG(PWM_BASE+0x204+((x)*0x20))\r
+#define PWM_CH_PERIOD(x) REG(PWM_BASE+0x208+((x)*0x20))\r
+#define PWM_CH_COUNTER(x) REG(PWM_BASE+0x20c+((x)*0x20))\r
+#define PWM_CH_UPDATE(x) REG(PWM_BASE+0x210+((x)*0x20))\r
+\r
+#define PWM_MODE_DIVA(x) ((x)<<0)\r
+#define PWM_MODE_PREA(x) ((x)<<8)\r
+#define PWM_MODE_DIVB(x) ((x)<<16)\r
+#define PWM_MODE_PREB(x) ((x)<<24)\r
+\r
+#define PWM_CHANNEL(x) (1<<(x))\r
+\r
+#define PWM_CH_MODE_PRESCALER(x) ((x)<<0)\r
+#define PWM_CH_MODE_PERIOD_CENTER_ALIGNED (1<<8)\r
+#define PWM_CH_MODE_POLARITY_STARTS_HIGH (1<<9)\r
+#define PWM_CH_MODE_UPDATE_UPDATES_PERIOD (1<<10)\r
+\r
+//-------------\r
+// Debug Unit\r
+\r
+#define DBG_BASE (0xfffff200)\r
+\r
+#define DBGU_CR REG(DBG_BASE+0x0000)\r
+#define DBGU_MR REG(DBG_BASE+0x0004)\r
+#define DBGU_IER REG(DBG_BASE+0x0008)\r
+#define DBGU_IDR REG(DBG_BASE+0x000C)\r
+#define DBGU_IMR REG(DBG_BASE+0x0010)\r
+#define DBGU_SR REG(DBG_BASE+0x0014)\r
+#define DBGU_RHR REG(DBG_BASE+0x0018)\r
+#define DBGU_THR REG(DBG_BASE+0x001C)\r
+#define DBGU_BRGR REG(DBG_BASE+0x0020)\r
+#define DBGU_CIDR REG(DBG_BASE+0x0040)\r
+#define DBGU_EXID REG(DBG_BASE+0x0044)\r
+#define DBGU_FNR REG(DBG_BASE+0x0048)\r
+\r
+//-------------\r
+// Embedded Flash Controller\r
+\r
+#define MC_BASE (0xffffff00)\r
+\r
+#define MC_FLASH_MODE0 REG(MC_BASE+0x60)\r
+#define MC_FLASH_COMMAND REG(MC_BASE+0x64)\r
+#define MC_FLASH_STATUS REG(MC_BASE+0x68)\r
+#define MC_FLASH_MODE1 REG(MC_BASE+0x70)\r
+\r
+#define MC_FLASH_MODE_READY_INTERRUPT_ENABLE (1<<0)\r
+#define MC_FLASH_MODE_LOCK_INTERRUPT_ENABLE (1<<2)\r
+#define MC_FLASH_MODE_PROG_ERROR_INTERRUPT_ENABLE (1<<3)\r
+#define MC_FLASH_MODE_NO_ERASE_BEFORE_PROGRAMMING (1<<7)\r
+#define MC_FLASH_MODE_FLASH_WAIT_STATES(x) ((x)<<8)\r
+#define MC_FLASH_MODE_MASTER_CLK_IN_MHZ(x) ((x)<<16)\r
+\r
+#define MC_FLASH_COMMAND_FCMD(x) ((x)<<0)\r
+#define MC_FLASH_COMMAND_PAGEN(x) ((x)<<8)\r
+#define MC_FLASH_COMMAND_KEY ((0x5a)<<24)\r
+\r
+#define FCMD_NOP 0x0\r
+#define FCMD_WRITE_PAGE 0x1\r
+#define FCMD_SET_LOCK_BIT 0x2\r
+#define FCMD_WRITE_PAGE_LOCK 0x3\r
+#define FCMD_CLEAR_LOCK_BIT 0x4\r
+#define FCMD_ERASE_ALL 0x8\r
+#define FCMD_SET_GP_NVM_BIT 0xb\r
+#define FCMD_SET_SECURITY_BIT 0xf\r
+\r
+#define MC_FLASH_STATUS_READY (1<<0)\r
+#define MC_FLASH_STATUS_LOCK_ERROR (1<<2)\r
+#define MC_FLASH_STATUS_PROGRAMMING_ERROR (1<<3)\r
+#define MC_FLASH_STATUS_SECURITY_BIT_ACTIVE (1<<4)\r
+#define MC_FLASH_STATUS_GP_NVM_ACTIVE_0 (1<<8)\r
+#define MC_FLASH_STATUS_GP_NVM_ACTIVE_1 (1<<9)\r
+#define MC_FLASH_STATUS_LOCK_ACTIVE(x) (1<<((x)+16))\r
+\r
+#define FLASH_PAGE_SIZE_BYTES 256\r
+#define FLASH_PAGE_COUNT 512\r
+\r
+//-------------\r
+// Watchdog Timer - 12 bit down counter, uses slow clock divided by 128 as source\r
+\r
+#define WDT_BASE (0xfffffd40)\r
+\r
+#define WDT_CONTROL REG(WDT_BASE+0x00)\r
+#define WDT_MODE REG(WDT_BASE+0x04)\r
+#define WDT_STATUS REG(WDT_BASE+0x08)\r
+\r
+#define WDT_HIT() WDT_CONTROL = 0xa5000001\r
+\r
+#define WDT_MODE_COUNT(x) ((x)<<0)\r
+#define WDT_MODE_INTERRUPT_ON_EVENT (1<<12)\r
+#define WDT_MODE_RESET_ON_EVENT_ENABLE (1<<13)\r
+#define WDT_MODE_RESET_ON_EVENT (1<<14)\r
+#define WDT_MODE_WATCHDOG_DELTA(x) ((x)<<16)\r
+#define WDT_MODE_HALT_IN_DEBUG_MODE (1<<28)\r
+#define WDT_MODE_HALT_IN_IDLE_MODE (1<<29)\r
+#define WDT_MODE_DISABLE (1<<15)\r
+\r
+//-------------\r
+// Parallel Input/Output Controller\r
+\r
+#define PIO_BASE (0xfffff400)\r
+\r
+#define PIO_ENABLE REG(PIO_BASE+0x000)\r
+#define PIO_DISABLE REG(PIO_BASE+0x004)\r
+#define PIO_STATUS REG(PIO_BASE+0x008)\r
+#define PIO_OUTPUT_ENABLE REG(PIO_BASE+0x010)\r
+#define PIO_OUTPUT_DISABLE REG(PIO_BASE+0x014)\r
+#define PIO_OUTPUT_STATUS REG(PIO_BASE+0x018)\r
+#define PIO_GLITCH_ENABLE REG(PIO_BASE+0x020)\r
+#define PIO_GLITCH_DISABLE REG(PIO_BASE+0x024)\r
+#define PIO_GLITCH_STATUS REG(PIO_BASE+0x028)\r
+#define PIO_OUTPUT_DATA_SET REG(PIO_BASE+0x030)\r
+#define PIO_OUTPUT_DATA_CLEAR REG(PIO_BASE+0x034)\r
+#define PIO_OUTPUT_DATA_STATUS REG(PIO_BASE+0x038)\r
+#define PIO_PIN_DATA_STATUS REG(PIO_BASE+0x03c)\r
+#define PIO_OPEN_DRAIN_ENABLE REG(PIO_BASE+0x050)\r
+#define PIO_OPEN_DRAIN_DISABLE REG(PIO_BASE+0x054)\r
+#define PIO_OPEN_DRAIN_STATUS REG(PIO_BASE+0x058)\r
+#define PIO_NO_PULL_UP_ENABLE REG(PIO_BASE+0x060)\r
+#define PIO_NO_PULL_UP_DISABLE REG(PIO_BASE+0x064)\r
+#define PIO_NO_PULL_UP_STATUS REG(PIO_BASE+0x068)\r
+#define PIO_PERIPHERAL_A_SEL REG(PIO_BASE+0x070)\r
+#define PIO_PERIPHERAL_B_SEL REG(PIO_BASE+0x074)\r
+#define PIO_PERIPHERAL_WHICH REG(PIO_BASE+0x078)\r
+#define PIO_OUT_WRITE_ENABLE REG(PIO_BASE+0x0a0)\r
+#define PIO_OUT_WRITE_DISABLE REG(PIO_BASE+0x0a4)\r
+#define PIO_OUT_WRITE_STATUS REG(PIO_BASE+0x0a8)\r
+\r
+//-------------\r
+// USB Device Port\r
+\r
+#define UDP_BASE (0xfffb0000)\r
+\r
+#define UDP_FRAME_NUMBER REG(UDP_BASE+0x0000)\r
+#define UDP_GLOBAL_STATE REG(UDP_BASE+0x0004)\r
+#define UDP_FUNCTION_ADDR REG(UDP_BASE+0x0008)\r
+#define UDP_INTERRUPT_ENABLE REG(UDP_BASE+0x0010)\r
+#define UDP_INTERRUPT_DISABLE REG(UDP_BASE+0x0014)\r
+#define UDP_INTERRUPT_MASK REG(UDP_BASE+0x0018)\r
+#define UDP_INTERRUPT_STATUS REG(UDP_BASE+0x001c)\r
+#define UDP_INTERRUPT_CLEAR REG(UDP_BASE+0x0020)\r
+#define UDP_RESET_ENDPOINT REG(UDP_BASE+0x0028)\r
+#define UDP_ENDPOINT_CSR(x) REG(UDP_BASE+0x0030+((x)*4))\r
+#define UDP_ENDPOINT_FIFO(x) REG(UDP_BASE+0x0050+((x)*4))\r
+#define UDP_TRANSCEIVER_CTRL REG(UDP_BASE+0x0074)\r
+\r
+#define UDP_GLOBAL_STATE_ADDRESSED (1<<0)\r
+#define UDP_GLOBAL_STATE_CONFIGURED (1<<1)\r
+#define UDP_GLOBAL_STATE_SEND_RESUME_ENABLED (1<<2)\r
+#define UDP_GLOBAL_STATE_RESUME_RECEIVED (1<<3)\r
+#define UDP_GLOBAL_STATE_REMOTE_WAKE_UP_ENABLED (1<<4)\r
+\r
+#define UDP_FUNCTION_ADDR_ENABLED (1<<8)\r
+\r
+#define UDP_INTERRUPT_ENDPOINT(x) (1<<(x))\r
+#define UDP_INTERRUPT_SUSPEND (1<<8)\r
+#define UDP_INTERRUPT_RESUME (1<<9)\r
+#define UDP_INTERRUPT_EXTERNAL_RESUME (1<<10)\r
+#define UDP_INTERRUPT_SOF (1<<11)\r
+#define UDP_INTERRUPT_END_OF_BUS_RESET (1<<12)\r
+#define UDP_INTERRUPT_WAKEUP (1<<13)\r
+\r
+#define UDP_RESET_ENDPOINT_NUMBER(x) (1<<(x))\r
+\r
+#define UDP_CSR_TX_PACKET_ACKED (1<<0)\r
+#define UDP_CSR_RX_PACKET_RECEIVED_BANK_0 (1<<1)\r
+#define UDP_CSR_RX_HAVE_READ_SETUP_DATA (1<<2)\r
+#define UDP_CSR_STALL_SENT (1<<3)\r
+#define UDP_CSR_TX_PACKET (1<<4)\r
+#define UDP_CSR_FORCE_STALL (1<<5)\r
+#define UDP_CSR_RX_PACKET_RECEIVED_BANK_1 (1<<6)\r
+#define UDP_CSR_CONTROL_DATA_DIR (1<<7)\r
+#define UDP_CSR_EPTYPE_CONTROL (0<<8)\r
+#define UDP_CSR_EPTYPE_ISOCHRON_OUT (1<<8)\r
+#define UDP_CSR_EPTYPE_ISOCHRON_IN (5<<8)\r
+#define UDP_CSR_EPTYPE_BULK_OUT (2<<8)\r
+#define UDP_CSR_EPTYPE_BULK_IN (6<<8)\r
+#define UDP_CSR_EPTYPE_INTERRUPT_OUT (3<<8)\r
+#define UDP_CSR_EPTYPE_INTERRUPT_IN (7<<8)\r
+#define UDP_CSR_IS_DATA1 (1<<11)\r
+#define UDP_CSR_ENABLE_EP (1<<15)\r
+#define UDP_CSR_BYTES_RECEIVED(x) (((x) >> 16) & 0x7ff)\r
+\r
+#define UDP_TRANSCEIVER_CTRL_DISABLE (1<<8)\r
+\r
+//-------------\r
+// Power Management Controller\r
+\r
+#define PMC_BASE (0xfffffc00)\r
+\r
+#define PMC_SYS_CLK_ENABLE REG(PMC_BASE+0x0000)\r
+#define PMC_SYS_CLK_DISABLE REG(PMC_BASE+0x0004)\r
+#define PMC_SYS_CLK_STATUS REG(PMC_BASE+0x0008)\r
+#define PMC_PERIPHERAL_CLK_ENABLE REG(PMC_BASE+0x0010)\r
+#define PMC_PERIPHERAL_CLK_DISABLE REG(PMC_BASE+0x0014)\r
+#define PMC_PERIPHERAL_CLK_STATUS REG(PMC_BASE+0x0018)\r
+#define PMC_MAIN_OSCILLATOR REG(PMC_BASE+0x0020)\r
+#define PMC_MAIN_CLK_FREQUENCY REG(PMC_BASE+0x0024)\r
+#define PMC_PLL REG(PMC_BASE+0x002c)\r
+#define PMC_MASTER_CLK REG(PMC_BASE+0x0030)\r
+#define PMC_PROGRAMMABLE_CLK_0 REG(PMC_BASE+0x0040)\r
+#define PMC_PROGRAMMABLE_CLK_1 REG(PMC_BASE+0x0044)\r
+#define PMC_INTERRUPT_ENABLE REG(PMC_BASE+0x0060)\r
+#define PMC_INTERRUPT_DISABLE REG(PMC_BASE+0x0064)\r
+#define PMC_INTERRUPT_STATUS REG(PMC_BASE+0x0068)\r
+#define PMC_INTERRUPT_MASK REG(PMC_BASE+0x006c)\r
+\r
+#define PMC_SYS_CLK_PROCESSOR_CLK (1<<0)\r
+#define PMC_SYS_CLK_UDP_CLK (1<<7)\r
+#define PMC_SYS_CLK_PROGRAMMABLE_CLK_0 (1<<8)\r
+#define PMC_SYS_CLK_PROGRAMMABLE_CLK_1 (1<<9)\r
+#define PMC_SYS_CLK_PROGRAMMABLE_CLK_2 (1<<10)\r
+\r
+#define PMC_MAIN_OSCILLATOR_STABILIZED (1<<0)\r
+#define PMC_MAIN_OSCILLATOR_PLL_LOCK (1<<2)\r
+#define PMC_MAIN_OSCILLATOR_MCK_READY (1<<3)\r
+#define PMC_MAIN_OSCILLATOR_ENABLE (1<<0)\r
+#define PMC_MAIN_OSCILLATOR_BYPASS (1<<1)\r
+#define PMC_MAIN_OSCILLATOR_STARTUP_DELAY(x) ((x)<<8)\r
+\r
+#define PMC_PLL_DIVISOR(x) (x)\r
+#define PMC_PLL_COUNT_BEFORE_LOCK(x) ((x)<<8)\r
+#define PMC_PLL_FREQUENCY_RANGE(x) ((x)<<14)\r
+#define PMC_PLL_MULTIPLIER(x) (((x)-1)<<16)\r
+#define PMC_PLL_USB_DIVISOR(x) ((x)<<28)\r
+\r
+#define PMC_CLK_SELECTION_PLL_CLOCK (3<<0)\r
+#define PMC_CLK_SELECTION_MAIN_CLOCK (1<<0)\r
+#define PMC_CLK_SELECTION_SLOW_CLOCK (0<<0)\r
+#define PMC_CLK_PRESCALE_DIV_1 (0<<2)\r
+#define PMC_CLK_PRESCALE_DIV_2 (1<<2)\r
+#define PMC_CLK_PRESCALE_DIV_4 (2<<2)\r
+#define PMC_CLK_PRESCALE_DIV_8 (3<<2)\r
+#define PMC_CLK_PRESCALE_DIV_16 (4<<2)\r
+#define PMC_CLK_PRESCALE_DIV_32 (5<<2)\r
+#define PMC_CLK_PRESCALE_DIV_64 (6<<2)\r
+\r
+//-------------\r
+// Serial Peripheral Interface (SPI)\r
+\r
+#define SPI_BASE (0xfffe0000)\r
+\r
+#define SPI_CONTROL REG(SPI_BASE+0x00)\r
+#define SPI_MODE REG(SPI_BASE+0x04)\r
+#define SPI_RX_DATA REG(SPI_BASE+0x08)\r
+#define SPI_TX_DATA REG(SPI_BASE+0x0c)\r
+#define SPI_STATUS REG(SPI_BASE+0x10)\r
+#define SPI_INTERRUPT_ENABLE REG(SPI_BASE+0x14)\r
+#define SPI_INTERRUPT_DISABLE REG(SPI_BASE+0x18)\r
+#define SPI_INTERRUPT_MASK REG(SPI_BASE+0x1c)\r
+#define SPI_FOR_CHIPSEL_0 REG(SPI_BASE+0x30)\r
+#define SPI_FOR_CHIPSEL_1 REG(SPI_BASE+0x34)\r
+#define SPI_FOR_CHIPSEL_2 REG(SPI_BASE+0x38)\r
+#define SPI_FOR_CHIPSEL_3 REG(SPI_BASE+0x3c)\r
+\r
+#define SPI_CONTROL_ENABLE (1<<0)\r
+#define SPI_CONTROL_DISABLE (1<<1)\r
+#define SPI_CONTROL_RESET (1<<7)\r
+#define SPI_CONTROL_LAST_TRANSFER (1<<24)\r
+\r
+#define SPI_MODE_MASTER (1<<0)\r
+#define SPI_MODE_VARIABLE_CHIPSEL (1<<1)\r
+#define SPI_MODE_CHIPSELS_DECODED (1<<2)\r
+#define SPI_MODE_USE_DIVIDED_CLOCK (1<<3)\r
+#define SPI_MODE_MODE_FAULT_DETECTION_OFF (1<<4)\r
+#define SPI_MODE_LOOPBACK (1<<7)\r
+#define SPI_MODE_CHIPSEL(x) ((x)<<16)\r
+#define SPI_MODE_DELAY_BETWEEN_CHIPSELS(x) ((x)<<24)\r
+\r
+#define SPI_RX_DATA_CHIPSEL(x) (((x)>>16)&0xf)\r
+\r
+#define SPI_TX_DATA_CHIPSEL(x) ((x)<<16)\r
+#define SPI_TX_DATA_LAST_TRANSFER (1<<24)\r
+\r
+#define SPI_STATUS_RECEIVE_FULL (1<<0)\r
+#define SPI_STATUS_TRANSMIT_EMPTY (1<<1)\r
+#define SPI_STATUS_MODE_FAULT (1<<2)\r
+#define SPI_STATUS_OVERRUN (1<<3)\r
+#define SPI_STATUS_END_OF_RX_BUFFER (1<<4)\r
+#define SPI_STATUS_END_OF_TX_BUFFER (1<<5)\r
+#define SPI_STATUS_RX_BUFFER_FULL (1<<6)\r
+#define SPI_STATUS_TX_BUFFER_EMPTY (1<<7)\r
+#define SPI_STATUS_NSS_RISING_DETECTED (1<<8)\r
+#define SPI_STATUS_TX_EMPTY (1<<9)\r
+#define SPI_STATUS_SPI_ENABLED (1<<16)\r
+\r
+#define SPI_FOR_CHIPSEL_INACTIVE_CLK_1 (1<<0)\r
+#define SPI_FOR_CHIPSEL_PHASE (1<<1)\r
+#define SPI_FOR_CHIPSEL_LEAVE_CHIPSEL_LOW (1<<3)\r
+#define SPI_FOR_CHIPSEL_BITS_IN_WORD(x) ((x)<<4)\r
+#define SPI_FOR_CHIPSEL_DIVISOR(x) ((x)<<8)\r
+#define SPI_FOR_CHIPSEL_DELAY_BEFORE_CLK(x) ((x)<<16)\r
+#define SPI_FOR_CHIPSEL_INTERWORD_DELAY(x) ((x)<<24)\r
+\r
+//-------------\r
+// Analog to Digital Converter\r
+\r
+#define ADC_BASE (0xfffd8000)\r
+\r
+#define ADC_CONTROL REG(ADC_BASE+0x00)\r
+#define ADC_MODE REG(ADC_BASE+0x04)\r
+#define ADC_CHANNEL_ENABLE REG(ADC_BASE+0x10)\r
+#define ADC_CHANNEL_DISABLE REG(ADC_BASE+0x14)\r
+#define ADC_CHANNEL_STATUS REG(ADC_BASE+0x18)\r
+#define ADC_STATUS REG(ADC_BASE+0x1c)\r
+#define ADC_LAST_CONVERTED_DATA REG(ADC_BASE+0x20)\r
+#define ADC_INTERRUPT_ENABLE REG(ADC_BASE+0x24)\r
+#define ADC_INTERRUPT_DISABLE REG(ADC_BASE+0x28)\r
+#define ADC_INTERRUPT_MASK REG(ADC_BASE+0x2c)\r
+#define ADC_CHANNEL_DATA(x) REG(ADC_BASE+0x30+(4*(x)))\r
+\r
+#define ADC_CONTROL_RESET (1<<0)\r
+#define ADC_CONTROL_START (1<<1)\r
+\r
+#define ADC_MODE_HW_TRIGGERS_ENABLED (1<<0)\r
+#define ADC_MODE_8_BIT_RESOLUTION (1<<4)\r
+#define ADC_MODE_SLEEP (1<<5)\r
+#define ADC_MODE_PRESCALE(x) ((x)<<8)\r
+#define ADC_MODE_STARTUP_TIME(x) ((x)<<16)\r
+#define ADC_MODE_SAMPLE_HOLD_TIME(x) ((x)<<24)\r
+\r
+#define ADC_CHANNEL(x) (1<<(x))\r
+\r
+#define ADC_END_OF_CONVERSION(x) (1<<(x))\r
+#define ADC_OVERRUN_ERROR(x) (1<<(8+(x)))\r
+#define ADC_DATA_READY (1<<16)\r
+#define ADC_GENERAL_OVERRUN (1<<17)\r
+#define ADC_END_OF_RX_BUFFER (1<<18)\r
+#define ADC_RX_BUFFER_FULL (1<<19)\r
+\r
+//-------------\r
+// Synchronous Serial Controller\r
+\r
+#define SSC_BASE (0xfffd4000)\r
+\r
+#define SSC_CONTROL REG(SSC_BASE+0x00)\r
+#define SSC_CLOCK_DIVISOR REG(SSC_BASE+0x04)\r
+#define SSC_RECEIVE_CLOCK_MODE REG(SSC_BASE+0x10)\r
+#define SSC_RECEIVE_FRAME_MODE REG(SSC_BASE+0x14)\r
+#define SSC_TRANSMIT_CLOCK_MODE REG(SSC_BASE+0x18)\r
+#define SSC_TRANSMIT_FRAME_MODE REG(SSC_BASE+0x1c)\r
+#define SSC_RECEIVE_HOLDING REG(SSC_BASE+0x20)\r
+#define SSC_TRANSMIT_HOLDING REG(SSC_BASE+0x24)\r
+#define SSC_RECEIVE_SYNC_HOLDING REG(SSC_BASE+0x30)\r
+#define SSC_TRANSMIT_SYNC_HOLDING REG(SSC_BASE+0x34)\r
+#define SSC_STATUS REG(SSC_BASE+0x40)\r
+#define SSC_INTERRUPT_ENABLE REG(SSC_BASE+0x44)\r
+#define SSC_INTERRUPT_DISABLE REG(SSC_BASE+0x48)\r
+#define SSC_INTERRUPT_MASK REG(SSC_BASE+0x4c)\r
+\r
+#define SSC_CONTROL_RX_ENABLE (1<<0)\r
+#define SSC_CONTROL_RX_DISABLE (1<<1)\r
+#define SSC_CONTROL_TX_ENABLE (1<<8)\r
+#define SSC_CONTROL_TX_DISABLE (1<<9)\r
+#define SSC_CONTROL_RESET (1<<15)\r
+\r
+#define SSC_CLOCK_MODE_SELECT(x) ((x)<<0)\r
+#define SSC_CLOCK_MODE_OUTPUT(x) ((x)<<2)\r
+#define SSC_CLOCK_MODE_INVERT (1<<5)\r
+#define SSC_CLOCK_MODE_START(x) ((x)<<8)\r
+#define SSC_CLOCK_MODE_START_DELAY(x) ((x)<<16)\r
+#define SSC_CLOCK_MODE_FRAME_PERIOD(x) ((x)<<24)\r
+\r
+#define SSC_FRAME_MODE_BITS_IN_WORD(x) (((x)-1)<<0)\r
+#define SSC_FRAME_MODE_LOOPBACK (1<<5) // for RX\r
+#define SSC_FRAME_MODE_DEFAULT_IS_1 (1<<5) // for TX\r
+#define SSC_FRAME_MODE_MSB_FIRST (1<<7)\r
+#define SSC_FRAME_MODE_WORDS_PER_TRANSFER(x) ((x)<<8)\r
+#define SSC_FRAME_MODE_FRAME_SYNC_LEN(x) ((x)<<16)\r
+#define SSC_FRAME_MODE_FRAME_SYNC_TYPE(x) ((x)<<20)\r
+#define SSC_FRAME_MODE_SYNC_DATA_ENABLE (1<<23) // for TX only\r
+#define SSC_FRAME_MODE_NEGATIVE_EDGE (1<<24)\r
+\r
+#define SSC_STATUS_TX_READY (1<<0)\r
+#define SSC_STATUS_TX_EMPTY (1<<1)\r
+#define SSC_STATUS_TX_ENDED (1<<2)\r
+#define SSC_STATUS_TX_BUF_EMPTY (1<<3)\r
+#define SSC_STATUS_RX_READY (1<<4)\r
+#define SSC_STATUS_RX_OVERRUN (1<<5)\r
+#define SSC_STATUS_RX_ENDED (1<<6)\r
+#define SSC_STATUS_RX_BUF_FULL (1<<7)\r
+#define SSC_STATUS_TX_SYNC_OCCURRED (1<<10)\r
+#define SSC_STATUS_RX_SYNC_OCCURRED (1<<11)\r
+#define SSC_STATUS_TX_ENABLED (1<<16)\r
+#define SSC_STATUS_RX_ENABLED (1<<17)\r
+\r
+//-------------\r
+// Peripheral DMA Controller\r
+//\r
+// There is one set of registers for every peripheral that supports DMA.\r
+\r
+#define PDC_RX_POINTER(x) REG((x)+0x100)\r
+#define PDC_RX_COUNTER(x) REG((x)+0x104)\r
+#define PDC_TX_POINTER(x) REG((x)+0x108)\r
+#define PDC_TX_COUNTER(x) REG((x)+0x10c)\r
+#define PDC_RX_NEXT_POINTER(x) REG((x)+0x110)\r
+#define PDC_RX_NEXT_COUNTER(x) REG((x)+0x114)\r
+#define PDC_TX_NEXT_POINTER(x) REG((x)+0x118)\r
+#define PDC_TX_NEXT_COUNTER(x) REG((x)+0x11c)\r
+#define PDC_CONTROL(x) REG((x)+0x120)\r
+#define PDC_STATUS(x) REG((x)+0x124)\r
+\r
+#define PDC_RX_ENABLE (1<<0)\r
+#define PDC_RX_DISABLE (1<<1)\r
+#define PDC_TX_ENABLE (1<<8)\r
+#define PDC_TX_DISABLE (1<<9)\r
+\r
+#endif\r
projects / proxmark3-svn / blobdiff