fix ATR length (#790)

[proxmark3-svn] / fpga / hi_read_tx.v

diff --git a/fpga/hi_read_tx.v b/fpga/hi_read_tx.v
index f12e64eb65c2f8fea1adf6eba8dd211a8ff33a61..819f1697ed7d4f74a47e8aa51e62dbf283c2e9b7 100644 (file)
--- a/fpga/hi_read_tx.v
+++ b/fpga/hi_read_tx.v
@@ -24,33 +24,36 @@ module hi_read_tx(
     output dbg;
     input shallow_modulation;
 
+// low frequency outputs, not relevant
+assign pwr_lo = 1'b0;
+assign pwr_oe2 = 1'b0;
+       
 // The high-frequency stuff. For now, for testing, just bring out the carrier,
 // and allow the ARM to modulate it over the SSP.
 reg pwr_hi;
 reg pwr_oe1;
-reg pwr_oe2;
 reg pwr_oe3;
 reg pwr_oe4;
+
 always @(ck_1356megb or ssp_dout or shallow_modulation)
 begin
     if(shallow_modulation)
     begin
         pwr_hi <= ck_1356megb;
-        pwr_oe1 <= ~ssp_dout;
-        pwr_oe2 <= ~ssp_dout;
-        pwr_oe3 <= ~ssp_dout;
-        pwr_oe4 <= 1'b0;
+        pwr_oe1 <= 1'b0;
+        pwr_oe3 <= 1'b0;
+        pwr_oe4 <= ssp_dout;
     end
     else
     begin
-        pwr_hi <= ck_1356megb & ssp_dout;
+        pwr_hi <= ck_1356megb & ~ssp_dout;
         pwr_oe1 <= 1'b0;
-        pwr_oe2 <= 1'b0;
         pwr_oe3 <= 1'b0;
         pwr_oe4 <= 1'b0;
     end
 end
 
+
 // Then just divide the 13.56 MHz clock down to produce appropriate clocks
 // for the synchronous serial port.
 
@@ -68,22 +71,8 @@ always @(negedge ssp_clk)
 
 assign ssp_frame = (hi_byte_div == 3'b000);
 
-// Implement a hysteresis to give out the received signal on
-// ssp_din. Sample at fc.
-assign adc_clk = ck_1356meg;
+assign ssp_din = 1'b0;
 
-// ADC data appears on the rising edge, so sample it on the falling edge
-reg after_hysteresis;
-always @(negedge adc_clk)
-begin
-    if(& adc_d[7:0]) after_hysteresis <= 1'b1;
-    else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;
-end
-
-
-assign ssp_din = after_hysteresis;
-
-assign pwr_lo = 1'b0;
-assign dbg = ssp_din;
+assign dbg = ssp_frame;
 
-endmodule
+endmodule
\ No newline at end of file