]> git.zerfleddert.de Git - proxmark3-svn/blobdiff - armsrc/fpgaloader.c
add l/h option to hw tune and optimize order of tuning
[proxmark3-svn] / armsrc / fpgaloader.c
index 88fdc4cfc08a6517e092ef2aa892936fdb447285..e211c12fbd5a7e5119b86d6196da954e1b0198ef 100644 (file)
-//-----------------------------------------------------------------------------\r
-// Routines to load the FPGA image, and then to configure the FPGA's major\r
-// mode once it is configured.\r
-//\r
-// Jonathan Westhues, April 2006\r
-//-----------------------------------------------------------------------------\r
-#include <proxmark3.h>\r
-#include "apps.h"\r
-\r
-//-----------------------------------------------------------------------------\r
-// Set up the Serial Peripheral Interface as master\r
-// Used to write the FPGA config word\r
-// May also be used to write to other SPI attached devices like an LCD\r
-//-----------------------------------------------------------------------------\r
-void SetupSpi(int mode)\r
-{\r
-       // PA10 -> SPI_NCS2 chip select (LCD)\r
-       // PA11 -> SPI_NCS0 chip select (FPGA)\r
-       // PA12 -> SPI_MISO Master-In Slave-Out\r
-       // PA13 -> SPI_MOSI Master-Out Slave-In\r
-       // PA14 -> SPI_SPCK Serial Clock\r
-\r
-       // Disable PIO control of the following pins, allows use by the SPI peripheral\r
-       PIO_DISABLE                      =      (1 << GPIO_NCS0)        |\r
-                                                       (1 << GPIO_NCS2)        |\r
-                                                       (1 << GPIO_MISO)        |\r
-                                                       (1 << GPIO_MOSI)        |\r
-                                                       (1 << GPIO_SPCK);\r
-\r
-       PIO_PERIPHERAL_A_SEL =  (1 << GPIO_NCS0)        |\r
-                                                       (1 << GPIO_MISO)        |\r
-                                                       (1 << GPIO_MOSI)        |\r
-                                                       (1 << GPIO_SPCK);\r
-\r
-       PIO_PERIPHERAL_B_SEL =  (1 << GPIO_NCS2);\r
-\r
-       //enable the SPI Peripheral clock\r
-       PMC_PERIPHERAL_CLK_ENABLE = (1<<PERIPH_SPI);\r
-       // Enable SPI\r
-       SPI_CONTROL = SPI_CONTROL_ENABLE;\r
-\r
-       switch (mode) {\r
-               case SPI_FPGA_MODE:\r
-                       SPI_MODE =\r
-                               ( 0 << 24)      |       // Delay between chip selects (take default: 6 MCK periods)\r
-                               (14 << 16)      |       // Peripheral Chip Select (selects FPGA SPI_NCS0 or PA11)\r
-                               ( 0 << 7)       |       // Local Loopback Disabled\r
-                               ( 1 << 4)       |       // Mode Fault Detection disabled\r
-                               ( 0 << 2)       |       // Chip selects connected directly to peripheral\r
-                               ( 0 << 1)       |       // Fixed Peripheral Select\r
-                               ( 1 << 0);              // Master Mode\r
-                       SPI_FOR_CHIPSEL_0 =\r
-                               ( 1 << 24)      |       // Delay between Consecutive Transfers (32 MCK periods)\r
-                               ( 1 << 16)      |       // Delay Before SPCK (1 MCK period)\r
-                               ( 6 << 8)       |       // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud\r
-                               ( 8 << 4)       |       // Bits per Transfer (16 bits)\r
-                               ( 0 << 3)       |       // Chip Select inactive after transfer\r
-                               ( 1 << 1)       |       // Clock Phase data captured on leading edge, changes on following edge\r
-                               ( 0 << 0);              // Clock Polarity inactive state is logic 0\r
-                       break;\r
-               case SPI_LCD_MODE:\r
-                       SPI_MODE =\r
-                               ( 0 << 24)      |       // Delay between chip selects (take default: 6 MCK periods)\r
-                               (11 << 16)      |       // Peripheral Chip Select (selects LCD SPI_NCS2 or PA10)\r
-                               ( 0 << 7)       |       // Local Loopback Disabled\r
-                               ( 1 << 4)       |       // Mode Fault Detection disabled\r
-                               ( 0 << 2)       |       // Chip selects connected directly to peripheral\r
-                               ( 0 << 1)       |       // Fixed Peripheral Select\r
-                               ( 1 << 0);              // Master Mode\r
-                       SPI_FOR_CHIPSEL_2 =\r
-                               ( 1 << 24)      |       // Delay between Consecutive Transfers (32 MCK periods)\r
-                               ( 1 << 16)      |       // Delay Before SPCK (1 MCK period)\r
-                               ( 6 << 8)       |       // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud\r
-                               ( 1 << 4)       |       // Bits per Transfer (9 bits)\r
-                               ( 0 << 3)       |       // Chip Select inactive after transfer\r
-                               ( 1 << 1)       |       // Clock Phase data captured on leading edge, changes on following edge\r
-                               ( 0 << 0);              // Clock Polarity inactive state is logic 0\r
-                       break;\r
-               default:                                // Disable SPI\r
-                       SPI_CONTROL = SPI_CONTROL_DISABLE;\r
-                       break;\r
-       }\r
-}\r
-\r
-//-----------------------------------------------------------------------------\r
-// Set up the synchronous serial port, with the one set of options that we\r
-// always use when we are talking to the FPGA. Both RX and TX are enabled.\r
-//-----------------------------------------------------------------------------\r
-void FpgaSetupSsc(void)\r
-{\r
-       // First configure the GPIOs, and get ourselves a clock.\r
-       PIO_PERIPHERAL_A_SEL =  (1 << GPIO_SSC_FRAME)   |\r
-                                                       (1 << GPIO_SSC_DIN)             |\r
-                                                       (1 << GPIO_SSC_DOUT)    |\r
-                                                       (1 << GPIO_SSC_CLK);\r
-       PIO_DISABLE = (1 << GPIO_SSC_DOUT);\r
-\r
-       PMC_PERIPHERAL_CLK_ENABLE = (1 << PERIPH_SSC);\r
-\r
-       // Now set up the SSC proper, starting from a known state.\r
-       SSC_CONTROL = SSC_CONTROL_RESET;\r
-\r
-       // RX clock comes from TX clock, RX starts when TX starts, data changes\r
-       // on RX clock rising edge, sampled on falling edge\r
-       SSC_RECEIVE_CLOCK_MODE = SSC_CLOCK_MODE_SELECT(1) | SSC_CLOCK_MODE_START(1);\r
-\r
-       // 8 bits per transfer, no loopback, MSB first, 1 transfer per sync\r
-       // pulse, no output sync, start on positive-going edge of sync\r
-       SSC_RECEIVE_FRAME_MODE = SSC_FRAME_MODE_BITS_IN_WORD(8) |\r
-               SSC_FRAME_MODE_MSB_FIRST | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);\r
-\r
-       // clock comes from TK pin, no clock output, outputs change on falling\r
-       // edge of TK, start on rising edge of TF\r
-       SSC_TRANSMIT_CLOCK_MODE = SSC_CLOCK_MODE_SELECT(2) |\r
-               SSC_CLOCK_MODE_START(5);\r
-\r
-       // tx framing is the same as the rx framing\r
-       SSC_TRANSMIT_FRAME_MODE = SSC_RECEIVE_FRAME_MODE;\r
-\r
-       SSC_CONTROL = SSC_CONTROL_RX_ENABLE | SSC_CONTROL_TX_ENABLE;\r
-}\r
-\r
-//-----------------------------------------------------------------------------\r
-// Set up DMA to receive samples from the FPGA. We will use the PDC, with\r
-// a single buffer as a circular buffer (so that we just chain back to\r
-// ourselves, not to another buffer). The stuff to manipulate those buffers\r
-// is in apps.h, because it should be inlined, for speed.\r
-//-----------------------------------------------------------------------------\r
-void FpgaSetupSscDma(BYTE *buf, int len)\r
-{\r
-       PDC_RX_POINTER(SSC_BASE) = (DWORD)buf;\r
-       PDC_RX_COUNTER(SSC_BASE) = len;\r
-       PDC_RX_NEXT_POINTER(SSC_BASE) = (DWORD)buf;\r
-       PDC_RX_NEXT_COUNTER(SSC_BASE) = len;\r
-       PDC_CONTROL(SSC_BASE) = PDC_RX_ENABLE;\r
-}\r
-\r
-// Download the fpga image starting at FpgaImage and with length FpgaImageLen DWORDs (e.g. 4 bytes)\r
-// If bytereversal is set: reverse the byte order in each 4-byte word\r
-static void DownloadFPGA(const DWORD *FpgaImage, DWORD FpgaImageLen, int bytereversal)\r
-{\r
-       int i, j;\r
-\r
-       PIO_OUTPUT_ENABLE = (1 << GPIO_FPGA_ON);\r
-       PIO_ENABLE = (1 << GPIO_FPGA_ON);\r
-       PIO_OUTPUT_DATA_SET = (1 << GPIO_FPGA_ON);\r
-\r
-       SpinDelay(50);\r
-\r
-       LED_D_ON();\r
-\r
-       HIGH(GPIO_FPGA_NPROGRAM);\r
-       LOW(GPIO_FPGA_CCLK);\r
-       LOW(GPIO_FPGA_DIN);\r
-       PIO_OUTPUT_ENABLE = (1 << GPIO_FPGA_NPROGRAM)   |\r
-                                               (1 << GPIO_FPGA_CCLK)           |\r
-                                               (1 << GPIO_FPGA_DIN);\r
-       SpinDelay(1);\r
-\r
-       LOW(GPIO_FPGA_NPROGRAM);\r
-       SpinDelay(50);\r
-       HIGH(GPIO_FPGA_NPROGRAM);\r
-\r
-       for(i = 0; i < FpgaImageLen; i++) {\r
-               DWORD v = FpgaImage[i];\r
-               unsigned char w;\r
-               for(j = 0; j < 4; j++) {\r
-                       if(!bytereversal) \r
-                               w = v >>(j*8);\r
-                       else\r
-                               w = v >>((3-j)*8);\r
-#define SEND_BIT(x) { if(w & (1<<x) ) HIGH(GPIO_FPGA_DIN); else LOW(GPIO_FPGA_DIN); HIGH(GPIO_FPGA_CCLK); LOW(GPIO_FPGA_CCLK); }\r
-                       SEND_BIT(7);\r
-                       SEND_BIT(6);\r
-                       SEND_BIT(5);\r
-                       SEND_BIT(4);\r
-                       SEND_BIT(3);\r
-                       SEND_BIT(2);\r
-                       SEND_BIT(1);\r
-                       SEND_BIT(0);\r
-               }\r
-       }\r
-\r
-       LED_D_OFF();\r
-}\r
-\r
-static char *bitparse_headers_start;\r
-static char *bitparse_bitstream_end;\r
-static int bitparse_initialized;\r
-/* Simple Xilinx .bit parser. The file starts with the fixed opaque byte sequence\r
- * 00 09 0f f0 0f f0 0f f0 0f f0 00 00 01\r
- * After that the format is 1 byte section type (ASCII character), 2 byte length\r
- * (big endian), <length> bytes content. Except for section 'e' which has 4 bytes\r
+//-----------------------------------------------------------------------------
+// Jonathan Westhues, April 2006
+// iZsh <izsh at fail0verflow.com>, 2014
+//
+// This code is licensed to you under the terms of the GNU GPL, version 2 or,
+// at your option, any later version. See the LICENSE.txt file for the text of
+// the license.
+//-----------------------------------------------------------------------------
+// Routines to load the FPGA image, and then to configure the FPGA's major
+// mode once it is configured.
+//-----------------------------------------------------------------------------
+
+#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>
+#include "fpgaloader.h"
+#include "proxmark3.h"
+#include "util.h"
+#include "string.h"
+#include "BigBuf.h"
+#include "zlib.h"
+
+extern void Dbprintf(const char *fmt, ...);
+
+// remember which version of the bitstream we have already downloaded to the FPGA
+static int downloaded_bitstream = FPGA_BITSTREAM_ERR;
+
+// this is where the bitstreams are located in memory:
+extern uint8_t _binary_obj_fpga_all_bit_z_start, _binary_obj_fpga_all_bit_z_end;
+
+static uint8_t *fpga_image_ptr = NULL;
+static uint32_t uncompressed_bytes_cnt;
+
+static const uint8_t _bitparse_fixed_header[] = {0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x00, 0x00, 0x01};
+#define FPGA_BITSTREAM_FIXED_HEADER_SIZE       sizeof(_bitparse_fixed_header)
+#define OUTPUT_BUFFER_LEN              80
+#define FPGA_INTERLEAVE_SIZE   288
+
+//-----------------------------------------------------------------------------
+// Set up the Serial Peripheral Interface as master
+// Used to write the FPGA config word
+// May also be used to write to other SPI attached devices like an LCD
+//-----------------------------------------------------------------------------
+void SetupSpi(int mode)
+{
+       // PA10 -> SPI_NCS2 chip select (LCD)
+       // PA11 -> SPI_NCS0 chip select (FPGA)
+       // PA12 -> SPI_MISO Master-In Slave-Out
+       // PA13 -> SPI_MOSI Master-Out Slave-In
+       // PA14 -> SPI_SPCK Serial Clock
+
+       // Disable PIO control of the following pins, allows use by the SPI peripheral
+       AT91C_BASE_PIOA->PIO_PDR =
+               GPIO_NCS0       |
+               GPIO_NCS2       |
+               GPIO_MISO       |
+               GPIO_MOSI       |
+               GPIO_SPCK;
+
+       AT91C_BASE_PIOA->PIO_ASR =
+               GPIO_NCS0       |
+               GPIO_MISO       |
+               GPIO_MOSI       |
+               GPIO_SPCK;
+
+       AT91C_BASE_PIOA->PIO_BSR = GPIO_NCS2;
+
+       //enable the SPI Peripheral clock
+       AT91C_BASE_PMC->PMC_PCER = (1<<AT91C_ID_SPI);
+       // Enable SPI
+       AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN;
+
+       switch (mode) {
+               case SPI_FPGA_MODE:
+                       AT91C_BASE_SPI->SPI_MR =
+                               ( 0 << 24)      |       // Delay between chip selects (take default: 6 MCK periods)
+                               (14 << 16)      |       // Peripheral Chip Select (selects FPGA SPI_NCS0 or PA11)
+                               ( 0 << 7)       |       // Local Loopback Disabled
+                               ( 1 << 4)       |       // Mode Fault Detection disabled
+                               ( 0 << 2)       |       // Chip selects connected directly to peripheral
+                               ( 0 << 1)       |       // Fixed Peripheral Select
+                               ( 1 << 0);              // Master Mode
+                       AT91C_BASE_SPI->SPI_CSR[0] =
+                               ( 1 << 24)      |       // Delay between Consecutive Transfers (32 MCK periods)
+                               ( 1 << 16)      |       // Delay Before SPCK (1 MCK period)
+                               ( 6 << 8)       |       // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
+                               ( 8 << 4)       |       // Bits per Transfer (16 bits)
+                               ( 0 << 3)       |       // Chip Select inactive after transfer
+                               ( 1 << 1)       |       // Clock Phase data captured on leading edge, changes on following edge
+                               ( 0 << 0);              // Clock Polarity inactive state is logic 0
+                       break;
+               case SPI_LCD_MODE:
+                       AT91C_BASE_SPI->SPI_MR =
+                               ( 0 << 24)      |       // Delay between chip selects (take default: 6 MCK periods)
+                               (11 << 16)      |       // Peripheral Chip Select (selects LCD SPI_NCS2 or PA10)
+                               ( 0 << 7)       |       // Local Loopback Disabled
+                               ( 1 << 4)       |       // Mode Fault Detection disabled
+                               ( 0 << 2)       |       // Chip selects connected directly to peripheral
+                               ( 0 << 1)       |       // Fixed Peripheral Select
+                               ( 1 << 0);              // Master Mode
+                       AT91C_BASE_SPI->SPI_CSR[2] =
+                               ( 1 << 24)      |       // Delay between Consecutive Transfers (32 MCK periods)
+                               ( 1 << 16)      |       // Delay Before SPCK (1 MCK period)
+                               ( 6 << 8)       |       // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
+                               ( 1 << 4)       |       // Bits per Transfer (9 bits)
+                               ( 0 << 3)       |       // Chip Select inactive after transfer
+                               ( 1 << 1)       |       // Clock Phase data captured on leading edge, changes on following edge
+                               ( 0 << 0);              // Clock Polarity inactive state is logic 0
+                       break;
+               default:                                // Disable SPI
+                       AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIDIS;
+                       break;
+       }
+}
+
+//-----------------------------------------------------------------------------
+// Set up the synchronous serial port, with the one set of options that we
+// always use when we are talking to the FPGA. Both RX and TX are enabled.
+//-----------------------------------------------------------------------------
+void FpgaSetupSsc(void)
+{
+       // First configure the GPIOs, and get ourselves a clock.
+       AT91C_BASE_PIOA->PIO_ASR =
+               GPIO_SSC_FRAME  |
+               GPIO_SSC_DIN    |
+               GPIO_SSC_DOUT   |
+               GPIO_SSC_CLK;
+       AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
+
+       AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_SSC);
+
+       // Now set up the SSC proper, starting from a known state.
+       AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
+
+       // RX clock comes from TX clock, RX starts when TX starts, data changes
+       // on RX clock rising edge, sampled on falling edge
+       AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(1) | SSC_CLOCK_MODE_START(1);
+
+       // 8 bits per transfer, no loopback, MSB first, 1 transfer per sync
+       // pulse, no output sync
+       AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(8) |     AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
+
+       // clock comes from TK pin, no clock output, outputs change on falling
+       // edge of TK, sample on rising edge of TK, start on positive-going edge of sync
+       AT91C_BASE_SSC->SSC_TCMR = SSC_CLOCK_MODE_SELECT(2) |   SSC_CLOCK_MODE_START(5);
+
+       // tx framing is the same as the rx framing
+       AT91C_BASE_SSC->SSC_TFMR = AT91C_BASE_SSC->SSC_RFMR;
+
+       AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
+}
+
+//-----------------------------------------------------------------------------
+// Set up DMA to receive samples from the FPGA. We will use the PDC, with
+// a single buffer as a circular buffer (so that we just chain back to
+// ourselves, not to another buffer). The stuff to manipulate those buffers
+// is in apps.h, because it should be inlined, for speed.
+//-----------------------------------------------------------------------------
+bool FpgaSetupSscDma(uint8_t *buf, int len)
+{
+       if (buf == NULL) {
+        return false;
+    }
+
+       AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;        // Disable DMA Transfer
+       AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) buf;           // transfer to this memory address
+       AT91C_BASE_PDC_SSC->PDC_RCR = len;                                      // transfer this many bytes
+       AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) buf;          // next transfer to same memory address
+       AT91C_BASE_PDC_SSC->PDC_RNCR = len;                                     // ... with same number of bytes
+       AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN;         // go!
+    
+    return true;
+}
+
+
+//----------------------------------------------------------------------------
+// Uncompress (inflate) the FPGA data. Returns one decompressed byte with
+// each call. 
+//----------------------------------------------------------------------------
+static int get_from_fpga_combined_stream(z_streamp compressed_fpga_stream, uint8_t *output_buffer)
+{
+       if (fpga_image_ptr == compressed_fpga_stream->next_out) {       // need more data
+               compressed_fpga_stream->next_out = output_buffer;
+               compressed_fpga_stream->avail_out = OUTPUT_BUFFER_LEN;
+               fpga_image_ptr = output_buffer;
+               int res = inflate(compressed_fpga_stream, Z_SYNC_FLUSH);
+               if (res != Z_OK) {
+                       Dbprintf("inflate returned: %d, %s", res, compressed_fpga_stream->msg);
+               }
+               if (res < 0) {
+                       return res;
+               }
+       }
+
+       uncompressed_bytes_cnt++;
+       
+       return *fpga_image_ptr++;
+}
+
+//----------------------------------------------------------------------------
+// Undo the interleaving of several FPGA config files. FPGA config files
+// are combined into one big file:
+// 288 bytes from FPGA file 1, followed by 288 bytes from FGPA file 2, etc.
+//----------------------------------------------------------------------------
+static int get_from_fpga_stream(int bitstream_version, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
+{
+       while((uncompressed_bytes_cnt / FPGA_INTERLEAVE_SIZE) % FPGA_BITSTREAM_MAX != (bitstream_version - 1)) {
+               // skip undesired data belonging to other bitstream_versions
+               get_from_fpga_combined_stream(compressed_fpga_stream, output_buffer);
+       }
+
+       return get_from_fpga_combined_stream(compressed_fpga_stream, output_buffer);
+       
+}
+
+
+static voidpf fpga_inflate_malloc(voidpf opaque, uInt items, uInt size)
+{
+       return BigBuf_malloc(items*size);
+}
+
+
+static void fpga_inflate_free(voidpf opaque, voidpf address)
+{
+       BigBuf_free();
+}
+
+
+//----------------------------------------------------------------------------
+// Initialize decompression of the respective (HF or LF) FPGA stream 
+//----------------------------------------------------------------------------
+static bool reset_fpga_stream(int bitstream_version, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
+{
+       uint8_t header[FPGA_BITSTREAM_FIXED_HEADER_SIZE];
+       
+       uncompressed_bytes_cnt = 0;
+       
+       // initialize z_stream structure for inflate:
+       compressed_fpga_stream->next_in = &_binary_obj_fpga_all_bit_z_start;
+       compressed_fpga_stream->avail_in = &_binary_obj_fpga_all_bit_z_start - &_binary_obj_fpga_all_bit_z_end;
+       compressed_fpga_stream->next_out = output_buffer;
+       compressed_fpga_stream->avail_out = OUTPUT_BUFFER_LEN;
+       compressed_fpga_stream->zalloc = &fpga_inflate_malloc;
+       compressed_fpga_stream->zfree = &fpga_inflate_free;
+
+       inflateInit2(compressed_fpga_stream, 0);
+
+       fpga_image_ptr = output_buffer;
+
+       for (uint16_t i = 0; i < FPGA_BITSTREAM_FIXED_HEADER_SIZE; i++) {
+               header[i] = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
+       }
+       
+       // Check for a valid .bit file (starts with _bitparse_fixed_header)
+       if(memcmp(_bitparse_fixed_header, header, FPGA_BITSTREAM_FIXED_HEADER_SIZE) == 0) {
+               return true;
+       } else {
+               return false;
+       }
+}
+
+
+static void DownloadFPGA_byte(unsigned char w)
+{
+#define SEND_BIT(x) { if(w & (1<<x) ) HIGH(GPIO_FPGA_DIN); else LOW(GPIO_FPGA_DIN); HIGH(GPIO_FPGA_CCLK); LOW(GPIO_FPGA_CCLK); }
+       SEND_BIT(7);
+       SEND_BIT(6);
+       SEND_BIT(5);
+       SEND_BIT(4);
+       SEND_BIT(3);
+       SEND_BIT(2);
+       SEND_BIT(1);
+       SEND_BIT(0);
+}
+
+// Download the fpga image starting at current stream position with length FpgaImageLen bytes
+static void DownloadFPGA(int bitstream_version, int FpgaImageLen, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
+{
+
+       Dbprintf("DownloadFPGA(len: %d)", FpgaImageLen);
+       
+       int i=0;
+
+       AT91C_BASE_PIOA->PIO_OER = GPIO_FPGA_ON;
+       AT91C_BASE_PIOA->PIO_PER = GPIO_FPGA_ON;
+       HIGH(GPIO_FPGA_ON);             // ensure everything is powered on
+
+       SpinDelay(50);
+
+       LED_D_ON();
+
+       // These pins are inputs
+    AT91C_BASE_PIOA->PIO_ODR =
+       GPIO_FPGA_NINIT |
+       GPIO_FPGA_DONE;
+       // PIO controls the following pins
+    AT91C_BASE_PIOA->PIO_PER =
+       GPIO_FPGA_NINIT |
+       GPIO_FPGA_DONE;
+       // Enable pull-ups
+       AT91C_BASE_PIOA->PIO_PPUER =
+               GPIO_FPGA_NINIT |
+               GPIO_FPGA_DONE;
+
+       // setup initial logic state
+       HIGH(GPIO_FPGA_NPROGRAM);
+       LOW(GPIO_FPGA_CCLK);
+       LOW(GPIO_FPGA_DIN);
+       // These pins are outputs
+       AT91C_BASE_PIOA->PIO_OER =
+               GPIO_FPGA_NPROGRAM      |
+               GPIO_FPGA_CCLK          |
+               GPIO_FPGA_DIN;
+
+       // enter FPGA configuration mode
+       LOW(GPIO_FPGA_NPROGRAM);
+       SpinDelay(50);
+       HIGH(GPIO_FPGA_NPROGRAM);
+
+       i=100000;
+       // wait for FPGA ready to accept data signal
+       while ((i) && ( !(AT91C_BASE_PIOA->PIO_PDSR & GPIO_FPGA_NINIT ) ) ) {
+               i--;
+       }
+
+       // crude error indicator, leave both red LEDs on and return
+       if (i==0){
+               LED_C_ON();
+               LED_D_ON();
+               return;
+       }
+
+       for(i = 0; i < FpgaImageLen; i++) {
+               int b = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
+               if (b < 0) {
+                       Dbprintf("Error %d during FpgaDownload", b);
+                       break;
+               }
+               DownloadFPGA_byte(b);
+       }
+       
+       // continue to clock FPGA until ready signal goes high
+       i=100000;
+       while ( (i--) && ( !(AT91C_BASE_PIOA->PIO_PDSR & GPIO_FPGA_DONE ) ) ) {
+               HIGH(GPIO_FPGA_CCLK);
+               LOW(GPIO_FPGA_CCLK);
+       }
+       // crude error indicator, leave both red LEDs on and return
+       if (i==0){
+               LED_C_ON();
+               LED_D_ON();
+               return;
+       }
+       LED_D_OFF();
+}
+
+
+/* Simple Xilinx .bit parser. The file starts with the fixed opaque byte sequence
+ * 00 09 0f f0 0f f0 0f f0 0f f0 00 00 01
+ * After that the format is 1 byte section type (ASCII character), 2 byte length
+ * (big endian), <length> bytes content. Except for section 'e' which has 4 bytes
  * length.
- */\r
-static const char _bitparse_fixed_header[] = {0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x00, 0x00, 0x01};\r
-static int bitparse_init(void * start_address, void *end_address)\r
-{\r
-       bitparse_initialized = 0;\r
-       \r
-       if(memcmp(_bitparse_fixed_header, start_address, sizeof(_bitparse_fixed_header)) != 0) {\r
-               return 0; /* Not matched */\r
-       } else {\r
-               bitparse_headers_start= ((char*)start_address) + sizeof(_bitparse_fixed_header);\r
-               bitparse_bitstream_end= (char*)end_address;\r
-               bitparse_initialized = 1;\r
-               return 1;\r
-       }\r
-}\r
-\r
-int bitparse_find_section(char section_name, void **section_start, unsigned int *section_length)\r
-{\r
-       char *pos = bitparse_headers_start;\r
-       int result = 0;\r
-\r
-       if(!bitparse_initialized) return 0;\r
-\r
-       while(pos < bitparse_bitstream_end) {\r
-               char current_name = *pos++;\r
-               unsigned int current_length = 0;\r
-               if(current_name < 'a' || current_name > 'e') {\r
-                       /* Strange section name, abort */\r
-                       break;\r
-               }\r
-               current_length = 0;\r
-               switch(current_name) {\r
-               case 'e':\r
-                       /* Four byte length field */\r
-                       current_length += (*pos++) << 24;\r
-                       current_length += (*pos++) << 16;\r
-               default: /* Fall through, two byte length field */\r
-                       current_length += (*pos++) << 8;\r
-                       current_length += (*pos++) << 0;\r
-               }\r
-               \r
-               if(current_name != 'e' && current_length > 255) {\r
-                       /* Maybe a parse error */\r
-                       break;\r
-               }\r
-               \r
-               if(current_name == section_name) {\r
-                       /* Found it */\r
-                       *section_start = pos;\r
-                       *section_length = current_length;\r
-                       result = 1;\r
-                       break;\r
-               }\r
-               \r
-               pos += current_length; /* Skip section */\r
-       }\r
-       \r
-       return result;\r
-}\r
-\r
-//-----------------------------------------------------------------------------\r
-// Find out which FPGA image format is stored in flash, then call DownloadFPGA\r
-// with the right parameters to download the image\r
-//-----------------------------------------------------------------------------\r
-extern char _binary_fpga_bit_start, _binary_fpga_bit_end;\r
-void FpgaDownloadAndGo(void)\r
-{\r
-       /* Check for the new flash image format: Should have the .bit file at &_binary_fpga_bit_start
-        */\r
-       if(bitparse_init(&_binary_fpga_bit_start, &_binary_fpga_bit_end)) {\r
-               /* Successfully initialized the .bit parser. Find the 'e' section and\r
-                * send its contents to the FPGA.
-                */\r
-               void *bitstream_start;\r
-               unsigned int bitstream_length;\r
-               if(bitparse_find_section('e', &bitstream_start, &bitstream_length)) {\r
-                       DownloadFPGA((DWORD *)bitstream_start, bitstream_length/4, 0);\r
-                       \r
-                       return; /* All done */\r
-               }\r
-       }\r
-       \r
-       /* Fallback for the old flash image format: Check for the magic marker 0xFFFFFFFF\r
-        * 0xAA995566 at address 0x2000. This is raw bitstream with a size of 336,768 bits \r
-        * = 10,524 DWORDs, stored as DWORDS e.g. little-endian in memory, but each DWORD\r
-        * is still to be transmitted in MSBit first order. Set the invert flag to indicate\r
-        * that the DownloadFPGA function should invert every 4 byte sequence when doing\r
-        * the bytewise download.
-        */\r
-       if( *(DWORD*)0x2000 == 0xFFFFFFFF && *(DWORD*)0x2004 == 0xAA995566 )\r
-               DownloadFPGA((DWORD *)0x2000, 10524, 1);\r
-}\r
-\r
-void FpgaGatherVersion(char *dst, int len)\r
-{\r
-       char *fpga_info; \r
-       unsigned int fpga_info_len;\r
-       dst[0] = 0;\r
-       if(!bitparse_find_section('e', (void**)&fpga_info, &fpga_info_len)) {\r
-               strncat(dst, "FPGA image: legacy image without version information", len-1);\r
-       } else {\r
-               strncat(dst, "FPGA image built", len-1);\r
-               /* USB packets only have 48 bytes data payload, so be terse */\r
-#if 0\r
-               if(bitparse_find_section('a', (void**)&fpga_info, &fpga_info_len) && fpga_info[fpga_info_len-1] == 0 ) {\r
-                       strncat(dst, " from ", len-1);\r
-                       strncat(dst, fpga_info, len-1);\r
-               }\r
-               if(bitparse_find_section('b', (void**)&fpga_info, &fpga_info_len) && fpga_info[fpga_info_len-1] == 0 ) {\r
-                       strncat(dst, " for ", len-1);\r
-                       strncat(dst, fpga_info, len-1);\r
-               }\r
-#endif\r
-               if(bitparse_find_section('c', (void**)&fpga_info, &fpga_info_len) && fpga_info[fpga_info_len-1] == 0 ) {\r
-                       strncat(dst, " on ", len-1);\r
-                       strncat(dst, fpga_info, len-1);\r
-               }\r
-               if(bitparse_find_section('d', (void**)&fpga_info, &fpga_info_len) && fpga_info[fpga_info_len-1] == 0 ) {\r
-                       strncat(dst, " at ", len-1);\r
-                       strncat(dst, fpga_info, len-1);\r
-               }\r
-       }\r
-}\r
-\r
-//-----------------------------------------------------------------------------\r
-// Send a 16 bit command/data pair to the FPGA.\r
-// The bit format is:  C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0\r
-// where C is the 4 bit command and D is the 12 bit data\r
-//-----------------------------------------------------------------------------\r
-void FpgaSendCommand(WORD cmd, WORD v)\r
-{\r
-       SetupSpi(SPI_FPGA_MODE);\r
-       while ((SPI_STATUS & SPI_STATUS_TX_EMPTY) == 0);                // wait for the transfer to complete\r
-       SPI_TX_DATA = SPI_CONTROL_LAST_TRANSFER | cmd | v;              // send the data\r
-}\r
-//-----------------------------------------------------------------------------\r
-// Write the FPGA setup word (that determines what mode the logic is in, read\r
-// vs. clone vs. etc.). This is now a special case of FpgaSendCommand() to\r
-// avoid changing this function's occurence everywhere in the source code.\r
-//-----------------------------------------------------------------------------\r
-void FpgaWriteConfWord(BYTE v)\r
-{\r
-       FpgaSendCommand(FPGA_CMD_SET_CONFREG, v);\r
-}\r
-\r
-//-----------------------------------------------------------------------------\r
-// Set up the CMOS switches that mux the ADC: four switches, independently\r
-// closable, but should only close one at a time. Not an FPGA thing, but\r
-// the samples from the ADC always flow through the FPGA.\r
-//-----------------------------------------------------------------------------\r
-void SetAdcMuxFor(int whichGpio)\r
-{\r
-       PIO_OUTPUT_ENABLE = (1 << GPIO_MUXSEL_HIPKD) |\r
-                                               (1 << GPIO_MUXSEL_LOPKD) |\r
-                                               (1 << GPIO_MUXSEL_LORAW) |\r
-                                               (1 << GPIO_MUXSEL_HIRAW);\r
-\r
-       PIO_ENABLE              =       (1 << GPIO_MUXSEL_HIPKD) |\r
-                                               (1 << GPIO_MUXSEL_LOPKD) |\r
-                                               (1 << GPIO_MUXSEL_LORAW) |\r
-                                               (1 << GPIO_MUXSEL_HIRAW);\r
-\r
-       LOW(GPIO_MUXSEL_HIPKD);\r
-       LOW(GPIO_MUXSEL_HIRAW);\r
-       LOW(GPIO_MUXSEL_LORAW);\r
-       LOW(GPIO_MUXSEL_LOPKD);\r
-\r
-       HIGH(whichGpio);\r
-}\r
+ */
+static int bitparse_find_section(int bitstream_version, char section_name, unsigned int *section_length, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
+{
+       int result = 0;
+       #define MAX_FPGA_BIT_STREAM_HEADER_SEARCH 100  // maximum number of bytes to search for the requested section
+       uint16_t numbytes = 0;
+       while(numbytes < MAX_FPGA_BIT_STREAM_HEADER_SEARCH) {
+               char current_name = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
+               numbytes++;
+               unsigned int current_length = 0;
+               if(current_name < 'a' || current_name > 'e') {
+                       /* Strange section name, abort */
+                       break;
+               }
+               current_length = 0;
+               switch(current_name) {
+               case 'e':
+                       /* Four byte length field */
+                       current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 24;
+                       current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 16;
+                       numbytes += 2;
+               default: /* Fall through, two byte length field */
+                       current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 8;
+                       current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 0;
+                       numbytes += 2;
+               }
+
+               if(current_name != 'e' && current_length > 255) {
+                       /* Maybe a parse error */
+                       break;
+               }
+
+               if(current_name == section_name) {
+                       /* Found it */
+                       *section_length = current_length;
+                       result = 1;
+                       break;
+               }
+
+               for (uint16_t i = 0; i < current_length && numbytes < MAX_FPGA_BIT_STREAM_HEADER_SEARCH; i++) {
+                       get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
+                       numbytes++;
+               }
+       }
+
+       return result;
+}
+
+
+//----------------------------------------------------------------------------
+// Check which FPGA image is currently loaded (if any). If necessary 
+// decompress and load the correct (HF or LF) image to the FPGA
+//----------------------------------------------------------------------------
+void FpgaDownloadAndGo(int bitstream_version)
+{
+       z_stream compressed_fpga_stream;
+       uint8_t output_buffer[OUTPUT_BUFFER_LEN];
+       
+       // check whether or not the bitstream is already loaded
+       if (downloaded_bitstream == bitstream_version)
+               return;
+
+       // make sure that we have enough memory to decompress
+       BigBuf_free();
+       
+       if (!reset_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer)) {
+               return;
+       }
+
+       unsigned int bitstream_length;
+       if(bitparse_find_section(bitstream_version, 'e', &bitstream_length, &compressed_fpga_stream, output_buffer)) {
+               DownloadFPGA(bitstream_version, bitstream_length, &compressed_fpga_stream, output_buffer);
+               downloaded_bitstream = bitstream_version;
+       }
+
+       inflateEnd(&compressed_fpga_stream);
+}      
+
+
+//-----------------------------------------------------------------------------
+// Gather version information from FPGA image. Needs to decompress the begin 
+// of the respective (HF or LF) image.
+// Note: decompression makes use of (i.e. overwrites) BigBuf[]. It is therefore
+// advisable to call this only once and store the results for later use.
+//-----------------------------------------------------------------------------
+void FpgaGatherVersion(int bitstream_version, char *dst, int len)
+{
+       unsigned int fpga_info_len;
+       char tempstr[40];
+       z_stream compressed_fpga_stream;
+       uint8_t output_buffer[OUTPUT_BUFFER_LEN];
+       
+       dst[0] = '\0';
+
+       // ensure that we can allocate enough memory for decompression:
+       BigBuf_free();
+
+       if (!reset_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer)) {
+               return;
+       }
+
+       if(bitparse_find_section(bitstream_version, 'a', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
+               for (uint16_t i = 0; i < fpga_info_len; i++) {
+                       char c = (char)get_from_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer);
+                       if (i < sizeof(tempstr)) {
+                               tempstr[i] = c;
+                       }
+               }
+               if (!memcmp("fpga_lf", tempstr, 7))
+                       strncat(dst, "LF ", len-1);
+               else if (!memcmp("fpga_hf", tempstr, 7))
+                       strncat(dst, "HF ", len-1);
+       }
+       strncat(dst, "FPGA image built", len-1);
+       if(bitparse_find_section(bitstream_version, 'b', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
+               strncat(dst, " for ", len-1);
+               for (uint16_t i = 0; i < fpga_info_len; i++) {
+                       char c = (char)get_from_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer);
+                       if (i < sizeof(tempstr)) {
+                               tempstr[i] = c;
+                       }
+               }
+               strncat(dst, tempstr, len-1);
+       }
+       if(bitparse_find_section(bitstream_version, 'c', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
+               strncat(dst, " on ", len-1);
+               for (uint16_t i = 0; i < fpga_info_len; i++) {
+                       char c = (char)get_from_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer);
+                       if (i < sizeof(tempstr)) {
+                               tempstr[i] = c;
+                       }
+               }
+               strncat(dst, tempstr, len-1);
+       }
+       if(bitparse_find_section(bitstream_version, 'd', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
+               strncat(dst, " at ", len-1);
+               for (uint16_t i = 0; i < fpga_info_len; i++) {
+                       char c = (char)get_from_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer);
+                       if (i < sizeof(tempstr)) {
+                               tempstr[i] = c;
+                       }
+               }
+               strncat(dst, tempstr, len-1);
+       }
+       
+       strncat(dst, "\n", len-1);
+
+       inflateEnd(&compressed_fpga_stream);
+}
+
+
+//-----------------------------------------------------------------------------
+// Send a 16 bit command/data pair to the FPGA.
+// The bit format is:  C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
+// where C is the 4 bit command and D is the 12 bit data
+//-----------------------------------------------------------------------------
+void FpgaSendCommand(uint16_t cmd, uint16_t v)
+{
+       SetupSpi(SPI_FPGA_MODE);
+       while ((AT91C_BASE_SPI->SPI_SR & AT91C_SPI_TXEMPTY) == 0);              // wait for the transfer to complete
+       AT91C_BASE_SPI->SPI_TDR = AT91C_SPI_LASTXFER | cmd | v;         // send the data
+}
+//-----------------------------------------------------------------------------
+// Write the FPGA setup word (that determines what mode the logic is in, read
+// vs. clone vs. etc.). This is now a special case of FpgaSendCommand() to
+// avoid changing this function's occurence everywhere in the source code.
+//-----------------------------------------------------------------------------
+void FpgaWriteConfWord(uint8_t v)
+{
+       FpgaSendCommand(FPGA_CMD_SET_CONFREG, v);
+}
+
+//-----------------------------------------------------------------------------
+// Set up the CMOS switches that mux the ADC: four switches, independently
+// closable, but should only close one at a time. Not an FPGA thing, but
+// the samples from the ADC always flow through the FPGA.
+//-----------------------------------------------------------------------------
+void SetAdcMuxFor(uint32_t whichGpio)
+{
+       AT91C_BASE_PIOA->PIO_OER =
+               GPIO_MUXSEL_HIPKD |
+               GPIO_MUXSEL_LOPKD |
+               GPIO_MUXSEL_LORAW |
+               GPIO_MUXSEL_HIRAW;
+
+       AT91C_BASE_PIOA->PIO_PER =
+               GPIO_MUXSEL_HIPKD |
+               GPIO_MUXSEL_LOPKD |
+               GPIO_MUXSEL_LORAW |
+               GPIO_MUXSEL_HIRAW;
+
+       LOW(GPIO_MUXSEL_HIPKD);
+       LOW(GPIO_MUXSEL_HIRAW);
+       LOW(GPIO_MUXSEL_LORAW);
+       LOW(GPIO_MUXSEL_LOPKD);
+
+       HIGH(whichGpio);
+}
+
+void Fpga_print_status(void)
+{
+       Dbprintf("Fgpa");
+       if(downloaded_bitstream == FPGA_BITSTREAM_HF) Dbprintf("  mode.............HF");
+       else if(downloaded_bitstream == FPGA_BITSTREAM_LF) Dbprintf("  mode.............LF");
+       else Dbprintf("  mode.............%d", downloaded_bitstream);
+}
+
+int FpgaGetCurrent() {
+       return downloaded_bitstream;
+}
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