FPGA changes ISO14443B:

[proxmark3-svn] / fpga / hi_read_rx_xcorr.v

diff --git a/fpga/hi_read_rx_xcorr.v b/fpga/hi_read_rx_xcorr.v
index 80e363275fd6ed6ab6f56c369e1b42827852022b..433d6736f1814c0f3cc529e807f8cfb70ed3c1eb 100644 (file)
--- a/fpga/hi_read_rx_xcorr.v
+++ b/fpga/hi_read_rx_xcorr.v
@@ -10,7 +10,7 @@ module hi_read_rx_xcorr(
     ssp_frame, ssp_din, ssp_dout, ssp_clk,
     cross_hi, cross_lo,
     dbg,
-    xcorr_is_848, snoop
+    xcorr_is_848, snoop, xcorr_quarter_freq
 );
     input pck0, ck_1356meg, ck_1356megb;
     output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
@@ -20,7 +20,7 @@ module hi_read_rx_xcorr(
     output ssp_frame, ssp_din, ssp_clk;
     input cross_hi, cross_lo;
     output dbg;
-    input xcorr_is_848, snoop;
+    input xcorr_is_848, snoop, xcorr_quarter_freq;
 
 // Carrier is steady on through this, unless we're snooping.
 assign pwr_hi = ck_1356megb & (~snoop);
@@ -28,19 +28,21 @@ assign pwr_oe1 = 1'b0;
 assign pwr_oe3 = 1'b0;
 assign pwr_oe4 = 1'b0;
 
-// Clock divider
-reg [0:0] fc_divider;
+reg [2:0] fc_div;
 always @(negedge ck_1356megb)
-    fc_divider <= fc_divider + 1;
-wire fc_div2 = fc_divider[0];
+    fc_div <= fc_div + 1;
 
-reg adc_clk;
-always @(ck_1356megb)
-       if (xcorr_is_848)
+(* clock_signal = "yes" *) reg adc_clk;                                // sample frequency, always 16 * fc
+always @(ck_1356megb, xcorr_is_848, xcorr_quarter_freq, fc_div)
+       if (xcorr_is_848 & ~xcorr_quarter_freq)                 // fc = 847.5 kHz, standard ISO14443B
                adc_clk <= ck_1356megb;
-       else
-               adc_clk <= fc_div2;
-
+       else if (~xcorr_is_848 & ~xcorr_quarter_freq)   // fc = 423.75 kHz 
+               adc_clk <= fc_div[0];
+       else if (xcorr_is_848 & xcorr_quarter_freq)             // fc = 211.875 kHz
+               adc_clk <= fc_div[1];
+       else                                                                                    // fc = 105.9375 kHz
+               adc_clk <= fc_div[2];
+               
 // When we're a reader, we just need to do the BPSK demod; but when we're an
 // eavesdropper, we also need to pick out the commands sent by the reader,
 // using AM. Do this the same way that we do it for the simulated tag.
@@ -67,14 +69,16 @@ begin
     end
 end
 
-// Let us report a correlation every 4 subcarrier cycles, or 4*16 samples,
+// Let us report a correlation every 4 subcarrier cycles, or 4*16=64 samples,
 // so we need a 6-bit counter.
 reg [5:0] corr_i_cnt;
 // And a couple of registers in which to accumulate the correlations.
-// we would add at most 32 times adc_d, the result can be held in 13 bits. 
-// Need one additional bit because it can be negative as well
-reg signed [13:0] corr_i_accum;
-reg signed [13:0] corr_q_accum;
+// We would add at most 32 times the difference between unmodulated and modulated signal. It should
+// be safe to assume that a tag will not be able to modulate the carrier signal by more than 25%.
+// 32 * 255 * 0,25 = 2040, which can be held in 11 bits. Add 1 bit for sign.
+reg signed [11:0] corr_i_accum;
+reg signed [11:0] corr_q_accum;
+// we will report maximum 8 significant bits
 reg signed [7:0] corr_i_out;
 reg signed [7:0] corr_q_out;
 // clock and frame signal for communication to ARM
@@ -84,7 +88,7 @@ reg ssp_frame;
 
 always @(negedge adc_clk)
 begin
-               corr_i_cnt <= corr_i_cnt + 1;
+       corr_i_cnt <= corr_i_cnt + 1;
 end            
                
 
@@ -98,16 +102,16 @@ begin
     begin
         if(snoop)
         begin
-                       // Send only 7 most significant bits of tag signal (signed), LSB is reader signal:
-            corr_i_out <= {corr_i_accum[13:7], after_hysteresis_prev_prev};
-            corr_q_out <= {corr_q_accum[13:7], after_hysteresis_prev};
+                       // Send 7 most significant bits of tag signal (signed), plus 1 bit reader signal
+            corr_i_out <= {corr_i_accum[11:5], after_hysteresis_prev_prev};
+            corr_q_out <= {corr_q_accum[11:5], after_hysteresis_prev};
                        after_hysteresis_prev_prev <= after_hysteresis;
         end
         else
         begin
-            // 8 most significant bits of tag signal
-            corr_i_out <= corr_i_accum[13:6];
-            corr_q_out <= corr_q_accum[13:6];
+            // 8 bits of tag signal
+            corr_i_out <= corr_i_accum[11:4];
+            corr_q_out <= corr_q_accum[11:4];
         end
 
         corr_i_accum <= adc_d;