Fix gcc10 compiler warnings

[proxmark3-svn] / armsrc / fpgaloader.c

diff --git a/armsrc/fpgaloader.c b/armsrc/fpgaloader.c
index e211c12fbd5a7e5119b86d6196da954e1b0198ef..61db66d32a0260577a84f679f65e6c220b3e7c16 100644 (file)
--- a/armsrc/fpgaloader.c
+++ b/armsrc/fpgaloader.c
@@ -10,20 +10,21 @@
 // mode once it is configured.
 //-----------------------------------------------------------------------------
 
 // mode once it is configured.
 //-----------------------------------------------------------------------------
 

+#include "fpgaloader.h"
+

 #include <stdint.h>
 #include <stddef.h>
 #include <stdbool.h>
 #include <stdint.h>
 #include <stddef.h>
 #include <stdbool.h>

-#include "fpgaloader.h"
+#include "apps.h"
+#include "fpga.h"

 #include "proxmark3.h"
 #include "util.h"
 #include "string.h"
 #include "BigBuf.h"
 #include "zlib.h"
 
 #include "proxmark3.h"
 #include "util.h"
 #include "string.h"
 #include "BigBuf.h"
 #include "zlib.h"
 

-extern void Dbprintf(const char *fmt, ...);
-

 // remember which version of the bitstream we have already downloaded to the FPGA
 // remember which version of the bitstream we have already downloaded to the FPGA

-static int downloaded_bitstream = FPGA_BITSTREAM_ERR;
+static int downloaded_bitstream = 0;

 
 // this is where the bitstreams are located in memory:
 extern uint8_t _binary_obj_fpga_all_bit_z_start, _binary_obj_fpga_all_bit_z_end;
 
 // this is where the bitstreams are located in memory:
 extern uint8_t _binary_obj_fpga_all_bit_z_start, _binary_obj_fpga_all_bit_z_end;


@@ -31,10 +32,7 @@ extern uint8_t _binary_obj_fpga_all_bit_z_start, _binary_obj_fpga_all_bit_z_end;
 static uint8_t *fpga_image_ptr = NULL;
 static uint32_t uncompressed_bytes_cnt;
 
 static uint8_t *fpga_image_ptr = NULL;
 static uint32_t uncompressed_bytes_cnt;
 

-static const uint8_t _bitparse_fixed_header[] = {0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x00, 0x00, 0x01};
-#define FPGA_BITSTREAM_FIXED_HEADER_SIZE       sizeof(_bitparse_fixed_header)
-#define OUTPUT_BUFFER_LEN              80
-#define FPGA_INTERLEAVE_SIZE   288
+#define OUTPUT_BUFFER_LEN       80

 
 //-----------------------------------------------------------------------------
 // Set up the Serial Peripheral Interface as master
 
 //-----------------------------------------------------------------------------
 // Set up the Serial Peripheral Interface as master


@@ -51,16 +49,16 @@ void SetupSpi(int mode)
 
        // Disable PIO control of the following pins, allows use by the SPI peripheral
        AT91C_BASE_PIOA->PIO_PDR =
 
        // Disable PIO control of the following pins, allows use by the SPI peripheral
        AT91C_BASE_PIOA->PIO_PDR =

-               GPIO_NCS0       |
-               GPIO_NCS2       |
-               GPIO_MISO       |
-               GPIO_MOSI       |
+               GPIO_NCS0   |
+               GPIO_NCS2   |
+               GPIO_MISO   |
+               GPIO_MOSI   |

                GPIO_SPCK;
 
        AT91C_BASE_PIOA->PIO_ASR =
                GPIO_SPCK;
 
        AT91C_BASE_PIOA->PIO_ASR =

-               GPIO_NCS0       |
-               GPIO_MISO       |
-               GPIO_MOSI       |
+               GPIO_NCS0   |
+               GPIO_MISO   |
+               GPIO_MOSI   |

                GPIO_SPCK;
 
        AT91C_BASE_PIOA->PIO_BSR = GPIO_NCS2;
                GPIO_SPCK;
 
        AT91C_BASE_PIOA->PIO_BSR = GPIO_NCS2;


@@ -73,57 +71,56 @@ void SetupSpi(int mode)
        switch (mode) {
                case SPI_FPGA_MODE:
                        AT91C_BASE_SPI->SPI_MR =
        switch (mode) {
                case SPI_FPGA_MODE:
                        AT91C_BASE_SPI->SPI_MR =

-                               ( 0 << 24)      |       // Delay between chip selects (take default: 6 MCK periods)
-                               (14 << 16)      |       // Peripheral Chip Select (selects FPGA SPI_NCS0 or PA11)
-                               ( 0 << 7)       |       // Local Loopback Disabled
-                               ( 1 << 4)       |       // Mode Fault Detection disabled
-                               ( 0 << 2)       |       // Chip selects connected directly to peripheral
-                               ( 0 << 1)       |       // Fixed Peripheral Select
-                               ( 1 << 0);              // Master Mode
+                               ( 0 << 24)  |   // Delay between chip selects (take default: 6 MCK periods)
+                               (14 << 16)  |   // Peripheral Chip Select (selects FPGA SPI_NCS0 or PA11)
+                               ( 0 << 7)   |   // Local Loopback Disabled
+                               ( 1 << 4)   |   // Mode Fault Detection disabled
+                               ( 0 << 2)   |   // Chip selects connected directly to peripheral
+                               ( 0 << 1)   |   // Fixed Peripheral Select
+                               ( 1 << 0);      // Master Mode

                        AT91C_BASE_SPI->SPI_CSR[0] =
                        AT91C_BASE_SPI->SPI_CSR[0] =

-                               ( 1 << 24)      |       // Delay between Consecutive Transfers (32 MCK periods)
-                               ( 1 << 16)      |       // Delay Before SPCK (1 MCK period)
-                               ( 6 << 8)       |       // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
-                               ( 8 << 4)       |       // Bits per Transfer (16 bits)
-                               ( 0 << 3)       |       // Chip Select inactive after transfer
-                               ( 1 << 1)       |       // Clock Phase data captured on leading edge, changes on following edge
-                               ( 0 << 0);              // Clock Polarity inactive state is logic 0
+                               ( 1 << 24)  |   // Delay between Consecutive Transfers (32 MCK periods)
+                               ( 1 << 16)  |   // Delay Before SPCK (1 MCK period)
+                               ( 6 << 8)   |   // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
+                               ( 8 << 4)   |   // Bits per Transfer (16 bits)
+                               ( 0 << 3)   |   // Chip Select inactive after transfer
+                               ( 1 << 1)   |   // Clock Phase data captured on leading edge, changes on following edge
+                               ( 0 << 0);      // Clock Polarity inactive state is logic 0

                        break;
                case SPI_LCD_MODE:
                        AT91C_BASE_SPI->SPI_MR =
                        break;
                case SPI_LCD_MODE:
                        AT91C_BASE_SPI->SPI_MR =

-                               ( 0 << 24)      |       // Delay between chip selects (take default: 6 MCK periods)
-                               (11 << 16)      |       // Peripheral Chip Select (selects LCD SPI_NCS2 or PA10)
-                               ( 0 << 7)       |       // Local Loopback Disabled
-                               ( 1 << 4)       |       // Mode Fault Detection disabled
-                               ( 0 << 2)       |       // Chip selects connected directly to peripheral
-                               ( 0 << 1)       |       // Fixed Peripheral Select
-                               ( 1 << 0);              // Master Mode
+                               ( 0 << 24)  |   // Delay between chip selects (take default: 6 MCK periods)
+                               (11 << 16)  |   // Peripheral Chip Select (selects LCD SPI_NCS2 or PA10)
+                               ( 0 << 7)   |   // Local Loopback Disabled
+                               ( 1 << 4)   |   // Mode Fault Detection disabled
+                               ( 0 << 2)   |   // Chip selects connected directly to peripheral
+                               ( 0 << 1)   |   // Fixed Peripheral Select
+                               ( 1 << 0);      // Master Mode

                        AT91C_BASE_SPI->SPI_CSR[2] =
                        AT91C_BASE_SPI->SPI_CSR[2] =

-                               ( 1 << 24)      |       // Delay between Consecutive Transfers (32 MCK periods)
-                               ( 1 << 16)      |       // Delay Before SPCK (1 MCK period)
-                               ( 6 << 8)       |       // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
-                               ( 1 << 4)       |       // Bits per Transfer (9 bits)
-                               ( 0 << 3)       |       // Chip Select inactive after transfer
-                               ( 1 << 1)       |       // Clock Phase data captured on leading edge, changes on following edge
-                               ( 0 << 0);              // Clock Polarity inactive state is logic 0
+                               ( 1 << 24)  |   // Delay between Consecutive Transfers (32 MCK periods)
+                               ( 1 << 16)  |   // Delay Before SPCK (1 MCK period)
+                               ( 6 << 8)   |   // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
+                               ( 1 << 4)   |   // Bits per Transfer (9 bits)
+                               ( 0 << 3)   |   // Chip Select inactive after transfer
+                               ( 1 << 1)   |   // Clock Phase data captured on leading edge, changes on following edge
+                               ( 0 << 0);      // Clock Polarity inactive state is logic 0

                        break;
                        break;

-               default:                                // Disable SPI
+               default:                // Disable SPI

                        AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIDIS;
                        break;
        }
 }
 
 //-----------------------------------------------------------------------------
                        AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIDIS;
                        break;
        }
 }
 
 //-----------------------------------------------------------------------------

-// Set up the synchronous serial port, with the one set of options that we
-// always use when we are talking to the FPGA. Both RX and TX are enabled.
+// Set up the synchronous serial port with the set of options that fits
+// the FPGA mode. Both RX and TX are always enabled.

 //-----------------------------------------------------------------------------
 //-----------------------------------------------------------------------------

-void FpgaSetupSsc(void)
-{
+void FpgaSetupSsc(uint16_t FPGA_mode) {

        // First configure the GPIOs, and get ourselves a clock.
        AT91C_BASE_PIOA->PIO_ASR =
        // First configure the GPIOs, and get ourselves a clock.
        AT91C_BASE_PIOA->PIO_ASR =

-               GPIO_SSC_FRAME  |
-               GPIO_SSC_DIN    |
-               GPIO_SSC_DOUT   |
+               GPIO_SSC_FRAME  |
+               GPIO_SSC_DIN    |
+               GPIO_SSC_DOUT   |

                GPIO_SSC_CLK;
        AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
 
                GPIO_SSC_CLK;
        AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
 


@@ -132,17 +129,21 @@ void FpgaSetupSsc(void)
        // Now set up the SSC proper, starting from a known state.
        AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
 
        // Now set up the SSC proper, starting from a known state.
        AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
 

-       // RX clock comes from TX clock, RX starts when TX starts, data changes
-       // on RX clock rising edge, sampled on falling edge
+       // RX clock comes from TX clock, RX starts on Transmit Start,
+       // data and frame signal is sampled on falling edge of RK

        AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(1) | SSC_CLOCK_MODE_START(1);
 
        AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(1) | SSC_CLOCK_MODE_START(1);
 

-       // 8 bits per transfer, no loopback, MSB first, 1 transfer per sync
+       // 8, 16 or 32 bits per transfer, no loopback, MSB first, 1 transfer per sync

        // pulse, no output sync
        // pulse, no output sync

-       AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(8) |     AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
+       if ((FPGA_mode & FPGA_MAJOR_MODE_MASK) == FPGA_MAJOR_MODE_HF_READER && FpgaGetCurrent() == FPGA_BITSTREAM_HF) {
+               AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(16) | AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
+       } else {
+               AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(8) | AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
+       }

 
 

-       // clock comes from TK pin, no clock output, outputs change on falling
-       // edge of TK, sample on rising edge of TK, start on positive-going edge of sync
-       AT91C_BASE_SSC->SSC_TCMR = SSC_CLOCK_MODE_SELECT(2) |   SSC_CLOCK_MODE_START(5);
+       // TX clock comes from TK pin, no clock output, outputs change on rising edge of TK, 
+       // TF (frame sync) is sampled on falling edge of TK, start TX on rising edge of TF
+       AT91C_BASE_SSC->SSC_TCMR = SSC_CLOCK_MODE_SELECT(2) | SSC_CLOCK_MODE_START(5);

 
        // tx framing is the same as the rx framing
        AT91C_BASE_SSC->SSC_TFMR = AT91C_BASE_SSC->SSC_RFMR;
 
        // tx framing is the same as the rx framing
        AT91C_BASE_SSC->SSC_TFMR = AT91C_BASE_SSC->SSC_RFMR;


@@ -156,44 +157,39 @@ void FpgaSetupSsc(void)
 // ourselves, not to another buffer). The stuff to manipulate those buffers
 // is in apps.h, because it should be inlined, for speed.
 //-----------------------------------------------------------------------------
 // ourselves, not to another buffer). The stuff to manipulate those buffers
 // is in apps.h, because it should be inlined, for speed.
 //-----------------------------------------------------------------------------

-bool FpgaSetupSscDma(uint8_t *buf, int len)
-{
-       if (buf == NULL) {
-        return false;
-    }
-
-       AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;        // Disable DMA Transfer
-       AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) buf;           // transfer to this memory address
-       AT91C_BASE_PDC_SSC->PDC_RCR = len;                                      // transfer this many bytes
-       AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) buf;          // next transfer to same memory address
-       AT91C_BASE_PDC_SSC->PDC_RNCR = len;                                     // ... with same number of bytes
-       AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN;         // go!
-    
-    return true;
+bool FpgaSetupSscDma(uint8_t *buf, uint16_t sample_count) {
+       if (buf == NULL) return false;
+
+       AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;        // Disable DMA Transfer
+       AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) buf;           // transfer to this memory address
+       AT91C_BASE_PDC_SSC->PDC_RCR = sample_count;             // transfer this many samples
+       AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) buf;          // next transfer to same memory address
+       AT91C_BASE_PDC_SSC->PDC_RNCR = sample_count;            // ... with same number of samples
+       AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN;         // go!
+       return true;

 }
 
 
 //----------------------------------------------------------------------------
 // Uncompress (inflate) the FPGA data. Returns one decompressed byte with
 }
 
 
 //----------------------------------------------------------------------------
 // Uncompress (inflate) the FPGA data. Returns one decompressed byte with

-// each call. 
+// each call.

 //----------------------------------------------------------------------------
 static int get_from_fpga_combined_stream(z_streamp compressed_fpga_stream, uint8_t *output_buffer)
 {
 //----------------------------------------------------------------------------
 static int get_from_fpga_combined_stream(z_streamp compressed_fpga_stream, uint8_t *output_buffer)
 {

-       if (fpga_image_ptr == compressed_fpga_stream->next_out) {       // need more data
+       if (fpga_image_ptr == compressed_fpga_stream->next_out) {   // need more data

                compressed_fpga_stream->next_out = output_buffer;
                compressed_fpga_stream->avail_out = OUTPUT_BUFFER_LEN;
                fpga_image_ptr = output_buffer;
                int res = inflate(compressed_fpga_stream, Z_SYNC_FLUSH);
                compressed_fpga_stream->next_out = output_buffer;
                compressed_fpga_stream->avail_out = OUTPUT_BUFFER_LEN;
                fpga_image_ptr = output_buffer;
                int res = inflate(compressed_fpga_stream, Z_SYNC_FLUSH);

-               if (res != Z_OK) {
+               if (res != Z_OK)

                        Dbprintf("inflate returned: %d, %s", res, compressed_fpga_stream->msg);
                        Dbprintf("inflate returned: %d, %s", res, compressed_fpga_stream->msg);

-               }
-               if (res < 0) {
+
+               if (res < 0)

                        return res;
                        return res;

-               }

        }
 
        uncompressed_bytes_cnt++;
        }
 
        uncompressed_bytes_cnt++;

-       
+

        return *fpga_image_ptr++;
 }
 
        return *fpga_image_ptr++;
 }
 


@@ -204,13 +200,13 @@ static int get_from_fpga_combined_stream(z_streamp compressed_fpga_stream, uint8
 //----------------------------------------------------------------------------
 static int get_from_fpga_stream(int bitstream_version, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
 {
 //----------------------------------------------------------------------------
 static int get_from_fpga_stream(int bitstream_version, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
 {

-       while((uncompressed_bytes_cnt / FPGA_INTERLEAVE_SIZE) % FPGA_BITSTREAM_MAX != (bitstream_version - 1)) {
+       while((uncompressed_bytes_cnt / FPGA_INTERLEAVE_SIZE) % fpga_bitstream_num != (bitstream_version - 1)) {

                // skip undesired data belonging to other bitstream_versions
                get_from_fpga_combined_stream(compressed_fpga_stream, output_buffer);
        }
 
        return get_from_fpga_combined_stream(compressed_fpga_stream, output_buffer);
                // skip undesired data belonging to other bitstream_versions
                get_from_fpga_combined_stream(compressed_fpga_stream, output_buffer);
        }
 
        return get_from_fpga_combined_stream(compressed_fpga_stream, output_buffer);

-       
+

 }
 
 
 }
 
 


@@ -222,22 +218,22 @@ static voidpf fpga_inflate_malloc(voidpf opaque, uInt items, uInt size)
 
 static void fpga_inflate_free(voidpf opaque, voidpf address)
 {
 
 static void fpga_inflate_free(voidpf opaque, voidpf address)
 {

-       BigBuf_free();
+       BigBuf_free(); BigBuf_Clear_ext(false);

 }
 
 
 //----------------------------------------------------------------------------
 }
 
 
 //----------------------------------------------------------------------------

-// Initialize decompression of the respective (HF or LF) FPGA stream 
+// Initialize decompression of the respective (HF or LF) FPGA stream

 //----------------------------------------------------------------------------
 static bool reset_fpga_stream(int bitstream_version, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
 {
        uint8_t header[FPGA_BITSTREAM_FIXED_HEADER_SIZE];
 //----------------------------------------------------------------------------
 static bool reset_fpga_stream(int bitstream_version, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
 {
        uint8_t header[FPGA_BITSTREAM_FIXED_HEADER_SIZE];

-       
+

        uncompressed_bytes_cnt = 0;
        uncompressed_bytes_cnt = 0;

-       
+

        // initialize z_stream structure for inflate:
        compressed_fpga_stream->next_in = &_binary_obj_fpga_all_bit_z_start;
        // initialize z_stream structure for inflate:
        compressed_fpga_stream->next_in = &_binary_obj_fpga_all_bit_z_start;

-       compressed_fpga_stream->avail_in = &_binary_obj_fpga_all_bit_z_start - &_binary_obj_fpga_all_bit_z_end;
+       compressed_fpga_stream->avail_in = &_binary_obj_fpga_all_bit_z_end - &_binary_obj_fpga_all_bit_z_start;

        compressed_fpga_stream->next_out = output_buffer;
        compressed_fpga_stream->avail_out = OUTPUT_BUFFER_LEN;
        compressed_fpga_stream->zalloc = &fpga_inflate_malloc;
        compressed_fpga_stream->next_out = output_buffer;
        compressed_fpga_stream->avail_out = OUTPUT_BUFFER_LEN;
        compressed_fpga_stream->zalloc = &fpga_inflate_malloc;


@@ -250,9 +246,9 @@ static bool reset_fpga_stream(int bitstream_version, z_streamp compressed_fpga_s
        for (uint16_t i = 0; i < FPGA_BITSTREAM_FIXED_HEADER_SIZE; i++) {
                header[i] = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
        }
        for (uint16_t i = 0; i < FPGA_BITSTREAM_FIXED_HEADER_SIZE; i++) {
                header[i] = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
        }

-       
-       // Check for a valid .bit file (starts with _bitparse_fixed_header)
-       if(memcmp(_bitparse_fixed_header, header, FPGA_BITSTREAM_FIXED_HEADER_SIZE) == 0) {
+
+       // Check for a valid .bit file (starts with bitparse_fixed_header)
+       if(memcmp(bitparse_fixed_header, header, FPGA_BITSTREAM_FIXED_HEADER_SIZE) == 0) {

                return true;
        } else {
                return false;
                return true;
        } else {
                return false;


@@ -277,26 +273,26 @@ static void DownloadFPGA_byte(unsigned char w)
 static void DownloadFPGA(int bitstream_version, int FpgaImageLen, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
 {
 
 static void DownloadFPGA(int bitstream_version, int FpgaImageLen, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
 {
 

-       Dbprintf("DownloadFPGA(len: %d)", FpgaImageLen);
-       
+       //Dbprintf("DownloadFPGA(len: %d)", FpgaImageLen);
+

        int i=0;
 
        AT91C_BASE_PIOA->PIO_OER = GPIO_FPGA_ON;
        AT91C_BASE_PIOA->PIO_PER = GPIO_FPGA_ON;
        int i=0;
 
        AT91C_BASE_PIOA->PIO_OER = GPIO_FPGA_ON;
        AT91C_BASE_PIOA->PIO_PER = GPIO_FPGA_ON;

-       HIGH(GPIO_FPGA_ON);             // ensure everything is powered on
+       HIGH(GPIO_FPGA_ON);     // ensure everything is powered on

 
        SpinDelay(50);
 
        LED_D_ON();
 
        // These pins are inputs
 
        SpinDelay(50);
 
        LED_D_ON();
 
        // These pins are inputs

-    AT91C_BASE_PIOA->PIO_ODR =
-       GPIO_FPGA_NINIT |
-       GPIO_FPGA_DONE;
+       AT91C_BASE_PIOA->PIO_ODR =
+               GPIO_FPGA_NINIT |
+               GPIO_FPGA_DONE;

        // PIO controls the following pins
        // PIO controls the following pins

-    AT91C_BASE_PIOA->PIO_PER =
-       GPIO_FPGA_NINIT |
-       GPIO_FPGA_DONE;
+       AT91C_BASE_PIOA->PIO_PER =
+               GPIO_FPGA_NINIT |
+               GPIO_FPGA_DONE;

        // Enable pull-ups
        AT91C_BASE_PIOA->PIO_PPUER =
                GPIO_FPGA_NINIT |
        // Enable pull-ups
        AT91C_BASE_PIOA->PIO_PPUER =
                GPIO_FPGA_NINIT |


@@ -308,8 +304,8 @@ static void DownloadFPGA(int bitstream_version, int FpgaImageLen, z_streamp comp
        LOW(GPIO_FPGA_DIN);
        // These pins are outputs
        AT91C_BASE_PIOA->PIO_OER =
        LOW(GPIO_FPGA_DIN);
        // These pins are outputs
        AT91C_BASE_PIOA->PIO_OER =

-               GPIO_FPGA_NPROGRAM      |
-               GPIO_FPGA_CCLK          |
+               GPIO_FPGA_NPROGRAM  |
+               GPIO_FPGA_CCLK      |

                GPIO_FPGA_DIN;
 
        // enter FPGA configuration mode
                GPIO_FPGA_DIN;
 
        // enter FPGA configuration mode


@@ -338,7 +334,7 @@ static void DownloadFPGA(int bitstream_version, int FpgaImageLen, z_streamp comp
                }
                DownloadFPGA_byte(b);
        }
                }
                DownloadFPGA_byte(b);
        }

-       
+

        // continue to clock FPGA until ready signal goes high
        i=100000;
        while ( (i--) && ( !(AT91C_BASE_PIOA->PIO_PDSR & GPIO_FPGA_DONE ) ) ) {
        // continue to clock FPGA until ready signal goes high
        i=100000;
        while ( (i--) && ( !(AT91C_BASE_PIOA->PIO_PDSR & GPIO_FPGA_DONE ) ) ) {


@@ -410,104 +406,40 @@ static int bitparse_find_section(int bitstream_version, char section_name, unsig
 
 
 //----------------------------------------------------------------------------
 
 
 //----------------------------------------------------------------------------

-// Check which FPGA image is currently loaded (if any). If necessary 
+// Check which FPGA image is currently loaded (if any). If necessary

 // decompress and load the correct (HF or LF) image to the FPGA
 //----------------------------------------------------------------------------
 void FpgaDownloadAndGo(int bitstream_version)
 {
        z_stream compressed_fpga_stream;
 // decompress and load the correct (HF or LF) image to the FPGA
 //----------------------------------------------------------------------------
 void FpgaDownloadAndGo(int bitstream_version)
 {
        z_stream compressed_fpga_stream;

-       uint8_t output_buffer[OUTPUT_BUFFER_LEN];
-       
+       uint8_t output_buffer[OUTPUT_BUFFER_LEN] = {0x00};
+

        // check whether or not the bitstream is already loaded
        // check whether or not the bitstream is already loaded

-       if (downloaded_bitstream == bitstream_version)
+       if (downloaded_bitstream == bitstream_version) {
+               FpgaEnableTracing();

                return;
                return;

+       }

 
        // make sure that we have enough memory to decompress
 
        // make sure that we have enough memory to decompress

-       BigBuf_free();
-       
+       BigBuf_free(); BigBuf_Clear_ext(false);
+

        if (!reset_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer)) {
                return;
        }
 
        unsigned int bitstream_length;
        if (!reset_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer)) {
                return;
        }
 
        unsigned int bitstream_length;

-       if(bitparse_find_section(bitstream_version, 'e', &bitstream_length, &compressed_fpga_stream, output_buffer)) {
+       if (bitparse_find_section(bitstream_version, 'e', &bitstream_length, &compressed_fpga_stream, output_buffer)) {

                DownloadFPGA(bitstream_version, bitstream_length, &compressed_fpga_stream, output_buffer);
                downloaded_bitstream = bitstream_version;
        }
 
        inflateEnd(&compressed_fpga_stream);
                DownloadFPGA(bitstream_version, bitstream_length, &compressed_fpga_stream, output_buffer);
                downloaded_bitstream = bitstream_version;
        }
 
        inflateEnd(&compressed_fpga_stream);

-}      
-
-
-//-----------------------------------------------------------------------------
-// Gather version information from FPGA image. Needs to decompress the begin 
-// of the respective (HF or LF) image.
-// Note: decompression makes use of (i.e. overwrites) BigBuf[]. It is therefore
-// advisable to call this only once and store the results for later use.
-//-----------------------------------------------------------------------------
-void FpgaGatherVersion(int bitstream_version, char *dst, int len)
-{
-       unsigned int fpga_info_len;
-       char tempstr[40];
-       z_stream compressed_fpga_stream;
-       uint8_t output_buffer[OUTPUT_BUFFER_LEN];
-       
-       dst[0] = '\0';
-
-       // ensure that we can allocate enough memory for decompression:
-       BigBuf_free();
-
-       if (!reset_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer)) {
-               return;
-       }

 
 

-       if(bitparse_find_section(bitstream_version, 'a', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
-               for (uint16_t i = 0; i < fpga_info_len; i++) {
-                       char c = (char)get_from_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer);
-                       if (i < sizeof(tempstr)) {
-                               tempstr[i] = c;
-                       }
-               }
-               if (!memcmp("fpga_lf", tempstr, 7))
-                       strncat(dst, "LF ", len-1);
-               else if (!memcmp("fpga_hf", tempstr, 7))
-                       strncat(dst, "HF ", len-1);
-       }
-       strncat(dst, "FPGA image built", len-1);
-       if(bitparse_find_section(bitstream_version, 'b', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
-               strncat(dst, " for ", len-1);
-               for (uint16_t i = 0; i < fpga_info_len; i++) {
-                       char c = (char)get_from_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer);
-                       if (i < sizeof(tempstr)) {
-                               tempstr[i] = c;
-                       }
-               }
-               strncat(dst, tempstr, len-1);
-       }
-       if(bitparse_find_section(bitstream_version, 'c', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
-               strncat(dst, " on ", len-1);
-               for (uint16_t i = 0; i < fpga_info_len; i++) {
-                       char c = (char)get_from_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer);
-                       if (i < sizeof(tempstr)) {
-                               tempstr[i] = c;
-                       }
-               }
-               strncat(dst, tempstr, len-1);
-       }
-       if(bitparse_find_section(bitstream_version, 'd', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
-               strncat(dst, " at ", len-1);
-               for (uint16_t i = 0; i < fpga_info_len; i++) {
-                       char c = (char)get_from_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer);
-                       if (i < sizeof(tempstr)) {
-                               tempstr[i] = c;
-                       }
-               }
-               strncat(dst, tempstr, len-1);
-       }
-       
-       strncat(dst, "\n", len-1);
+       // turn off antenna
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);

 
 

-       inflateEnd(&compressed_fpga_stream);
+       // free eventually allocated BigBuf memory
+       BigBuf_free(); BigBuf_Clear_ext(false);

 }
 
 
 }
 
 


@@ -516,22 +448,32 @@ void FpgaGatherVersion(int bitstream_version, char *dst, int len)
 // The bit format is:  C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
 // where C is the 4 bit command and D is the 12 bit data
 //-----------------------------------------------------------------------------
 // The bit format is:  C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
 // where C is the 4 bit command and D is the 12 bit data
 //-----------------------------------------------------------------------------

-void FpgaSendCommand(uint16_t cmd, uint16_t v)
-{
+void FpgaSendCommand(uint16_t cmd, uint16_t v) {

        SetupSpi(SPI_FPGA_MODE);
        SetupSpi(SPI_FPGA_MODE);

-       while ((AT91C_BASE_SPI->SPI_SR & AT91C_SPI_TXEMPTY) == 0);              // wait for the transfer to complete
-       AT91C_BASE_SPI->SPI_TDR = AT91C_SPI_LASTXFER | cmd | v;         // send the data
+       AT91C_BASE_SPI->SPI_TDR = AT91C_SPI_LASTXFER | cmd | v;     // write the data to be sent
+       while ((AT91C_BASE_SPI->SPI_SR & AT91C_SPI_TXEMPTY) == 0);  // wait for the transfer to complete

 }
 }

+

 //-----------------------------------------------------------------------------
 // Write the FPGA setup word (that determines what mode the logic is in, read
 // vs. clone vs. etc.). This is now a special case of FpgaSendCommand() to
 // avoid changing this function's occurence everywhere in the source code.
 //-----------------------------------------------------------------------------
 //-----------------------------------------------------------------------------
 // Write the FPGA setup word (that determines what mode the logic is in, read
 // vs. clone vs. etc.). This is now a special case of FpgaSendCommand() to
 // avoid changing this function's occurence everywhere in the source code.
 //-----------------------------------------------------------------------------

-void FpgaWriteConfWord(uint8_t v)
-{
+void FpgaWriteConfWord(uint16_t v) {

        FpgaSendCommand(FPGA_CMD_SET_CONFREG, v);
 }
 
        FpgaSendCommand(FPGA_CMD_SET_CONFREG, v);
 }
 

+//-----------------------------------------------------------------------------
+// enable/disable FPGA internal tracing
+//-----------------------------------------------------------------------------
+void FpgaEnableTracing(void) {
+       FpgaSendCommand(FPGA_CMD_TRACE_ENABLE, 1);
+}
+
+void FpgaDisableTracing(void) {
+       FpgaSendCommand(FPGA_CMD_TRACE_ENABLE, 0);
+}
+

 //-----------------------------------------------------------------------------
 // Set up the CMOS switches that mux the ADC: four switches, independently
 // closable, but should only close one at a time. Not an FPGA thing, but
 //-----------------------------------------------------------------------------
 // Set up the CMOS switches that mux the ADC: four switches, independently
 // closable, but should only close one at a time. Not an FPGA thing, but


@@ -559,12 +501,9 @@ void SetAdcMuxFor(uint32_t whichGpio)
        HIGH(whichGpio);
 }
 
        HIGH(whichGpio);
 }
 

-void Fpga_print_status(void)
-{
-       Dbprintf("Fgpa");
-       if(downloaded_bitstream == FPGA_BITSTREAM_HF) Dbprintf("  mode.............HF");
-       else if(downloaded_bitstream == FPGA_BITSTREAM_LF) Dbprintf("  mode.............LF");
-       else Dbprintf("  mode.............%d", downloaded_bitstream);
+void Fpga_print_status(void) {
+       Dbprintf("Currently loaded FPGA image:");
+       Dbprintf("  %s", fpga_version_information[downloaded_bitstream-1]);

 }
 
 int FpgaGetCurrent() {
 }
 
 int FpgaGetCurrent() {