THIS REQUIRES A BOOTROM UPDATE!! To save FPGA area, split the LF and HF bitstreams...

[proxmark3-svn] / fpga / lo_edge_detect.v

diff --git a/fpga/lo_edge_detect.v b/fpga/lo_edge_detect.v
index 8458ee6929ae8429e05ab11834ba9f1a172c252c..af600b833ac26ab28735ef5a397d974604782fc7 100644 (file)
--- a/fpga/lo_edge_detect.v
+++ b/fpga/lo_edge_detect.v
@@ -7,34 +7,18 @@
 //-----------------------------------------------------------------------------
 
 module lo_edge_detect(
-    pck0, ck_1356meg, ck_1356megb,
-    pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
-    adc_d, adc_clk,
-    ssp_frame, ssp_din, ssp_dout, ssp_clk,
-    cross_hi, cross_lo,
-    dbg,
-         divisor,
-               lf_field
+       input pck0, input [7:0] pck_cnt, input pck_divclk,
+       output pwr_lo, output pwr_hi,
+       output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
+       input [7:0] adc_d, output adc_clk,
+       output ssp_frame, input ssp_dout, output ssp_clk,
+       input cross_lo,
+       output dbg,
+       input lf_field
 );
-    input pck0, ck_1356meg, ck_1356megb;
-    output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
-    input [7:0] adc_d;
-    output adc_clk;
-    input ssp_dout;
-    output ssp_frame, ssp_din, ssp_clk;
-    input cross_hi, cross_lo;
-    output dbg;
-         input [7:0] divisor;
-               input lf_field;
 
-// Divide the clock to be used for the ADC
-reg [7:0] pck_divider;
-reg clk_state;
-
-wire tag_modulation; 
-assign tag_modulation = ssp_dout & !lf_field;
-wire reader_modulation; 
-assign reader_modulation = !ssp_dout & lf_field & clk_state;
+wire tag_modulation = ssp_dout & !lf_field;
+wire reader_modulation = !ssp_dout & lf_field & pck_divclk;
 
 // No logic, straight through.
 assign pwr_oe1 = 1'b0; // not used in LF mode
@@ -46,20 +30,7 @@ assign pwr_lo = reader_modulation;
 assign pwr_hi = 1'b0;
 assign dbg = ssp_frame;
 
-always @(posedge pck0)
-begin
-       if(pck_divider == divisor[7:0])
-               begin
-                       pck_divider <= 8'd0;
-                       clk_state = !clk_state;
-               end
-       else
-       begin
-               pck_divider <= pck_divider + 1;
-       end
-end
-
-assign adc_clk = ~clk_state;
+assign adc_clk = ~pck_divclk;
 
 // Toggle the output with hysteresis
 //  Set to high if the ADC value is above 200
@@ -70,7 +41,7 @@ reg output_state;
 
 always @(posedge pck0)
 begin
-       if((pck_divider == 8'd7) && !clk_state) begin
+       if((pck_cnt == 8'd7) && !pck_divclk) begin
                is_high = (adc_d >= 8'd190);
                is_low = (adc_d <= 8'd70);
        end