ReaderIClass(c->arg[0]);
break;
case CMD_READER_ICLASS_REPLAY:
- ReaderIClass_Replay(c->arg[0], c->d.asBytes);
+ ReaderIClass_Replay(c->arg[0], c->d.asBytes);
break;
- case CMD_ICLASS_EML_MEMSET:
+ case CMD_ICLASS_EML_MEMSET:
emlSet(c->d.asBytes,c->arg[0], c->arg[1]);
break;
+ case CMD_ICLASS_WRITEBLOCK:
+ iClass_WriteBlock(c->arg[0], c->d.asBytes);
+ break;
+ case CMD_ICLASS_READCHECK: // auth step 1
+ iClass_ReadCheck(c->arg[0], c->arg[1]);
+ break;
+ case CMD_ICLASS_READBLOCK:
+ iClass_ReadBlk(c->arg[0]);
+ break;
+ case CMD_ICLASS_AUTHENTICATION: //check
+ iClass_Authentication(c->d.asBytes);
+ break;
+ case CMD_ICLASS_DUMP:
+ iClass_Dump(c->arg[0], c->arg[1]);
+ break;
+ case CMD_ICLASS_CLONE:
+ iClass_Clone(c->arg[0], c->arg[1], c->d.asBytes);
+ break;
+#endif
+#ifdef WITH_HFSNOOP
+ case CMD_HF_SNIFFER:
+ HfSnoop(c->arg[0], c->arg[1]);
+ break;
#endif
case CMD_BUFF_CLEAR:
AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_PCK0;
// PCK0 is PLL clock / 4 = 96Mhz / 4 = 24Mhz
AT91C_BASE_PMC->PMC_PCKR[0] = AT91C_PMC_CSS_PLL_CLK |
- AT91C_PMC_PRES_CLK_4;
+ AT91C_PMC_PRES_CLK_4; // 4 for 24Mhz pck0, 2 for 48 MHZ pck0
AT91C_BASE_PIOA->PIO_OER = GPIO_PCK0;
// Reset SPI