Fix some printf/scanf format strings

[proxmark3-svn] / armsrc / legicrf.c

diff --git a/armsrc/legicrf.c b/armsrc/legicrf.c
index a8c0cd114b39c447bb825ec8af10e62370984dec..71ff0321c546208fbda0928bfadaf3184f09c328 100644 (file)
--- a/armsrc/legicrf.c
+++ b/armsrc/legicrf.c
@@ -1,360 +1,458 @@
-/*
- * LEGIC RF simulation code
- *  
- * (c) 2009 Henryk Plötz <henryk@ploetzli.ch>
- */
+//-----------------------------------------------------------------------------
+// (c) 2009 Henryk Plötz <henryk@ploetzli.ch>
+//     2016 Iceman
+//     2018 AntiCat
+//
+// This code is licensed to you under the terms of the GNU GPL, version 2 or,
+// at your option, any later version. See the LICENSE.txt file for the text of
+// the license.
+//-----------------------------------------------------------------------------
+// LEGIC RF simulation code
+//-----------------------------------------------------------------------------

 
 

-#include <proxmark3.h>
+#include "legicrf.h"

 
 

+#include "proxmark3.h"

 #include "apps.h"
 #include "apps.h"

-#include "legicrf.h"
-#include "unistd.h"
-#include "stdint.h"
-
-static struct legic_frame {
-       int bits;
-       uint16_t data;
-} current_frame;
-AT91PS_TC timer;
-
-static void setup_timer(void)
-{
-       /* Set up Timer 1 to use for measuring time between pulses. Since we're bit-banging
-        * this it won't be terribly accurate but should be good enough.
-        */
-       AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
-       timer = AT91C_BASE_TC1;
-       timer->TC_CCR = AT91C_TC_CLKDIS;
-       timer->TC_CMR = TC_CMR_TCCLKS_TIMER_CLOCK3;
-       timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
-
-/* At TIMER_CLOCK3 (MCK/32) */
-#define        RWD_TIME_1 150     /* RWD_TIME_PAUSE off, 80us on = 100us */
-#define RWD_TIME_0 90      /* RWD_TIME_PAUSE off, 40us on = 60us */
-#define RWD_TIME_PAUSE 30  /* 20us */
-#define RWD_TIME_FUZZ 20   /* rather generous 13us, since the peak detector + hysteresis fuzz quite a bit */
-#define TAG_TIME_BIT 150   /* 100us for every bit */
-#define TAG_TIME_WAIT 490  /* time from RWD frame end to tag frame start, experimentally determined */
+#include "usb_cdc.h"
+#include "util.h"
+#include "string.h"
+#include "legic_prng.h"
+#include "legic.h"
+#include "crc.h"
+#include "fpgaloader.h"
+
+static legic_card_select_t card;/* metadata of currently selected card */
+static crc_t legic_crc;
+
+//-----------------------------------------------------------------------------
+// Frame timing and pseudorandom number generator
+//
+// The Prng is forwarded every 100us (TAG_BIT_PERIOD), except when the reader is
+// transmitting. In that case the prng has to be forwarded every bit transmitted:
+//  - 60us for a 0 (RWD_TIME_0)
+//  - 100us for a 1 (RWD_TIME_1)
+//
+// The data dependent timing makes writing comprehensible code significantly
+// harder. The current aproach forwards the prng data based if there is data on
+// air and time based, using GET_TICKS, during computational and wait periodes.
+//
+// To not have the necessity to calculate/guess exection time dependend timeouts
+// tx_frame and rx_frame use a shared timestamp to coordinate tx and rx timeslots.
+//-----------------------------------------------------------------------------
+
+static uint32_t last_frame_end; /* ts of last bit of previews rx or tx frame */
+
+#define RWD_TIME_PAUSE       30 /* 20us */
+#define RWD_TIME_1          150 /* READER_TIME_PAUSE 20us off + 80us on = 100us */
+#define RWD_TIME_0           90 /* READER_TIME_PAUSE 20us off + 40us on = 60us */
+#define RWD_FRAME_WAIT      330 /* 220us from TAG frame end to READER frame start */
+#define TAG_FRAME_WAIT      495 /* 330us from READER frame end to TAG frame start */
+#define TAG_BIT_PERIOD      150 /* 100us */
+#define TAG_WRITE_TIMEOUT    60 /* 40 * 100us (write should take at most 3.6ms) */
+
+#define LEGIC_READ         0x01 /* Read Command */
+#define LEGIC_WRITE        0x00 /* Write Command */
+
+#define SESSION_IV         0x55 /* An arbitrary chose session IV, all shoud work */
+#define OFFSET_LOG         1024 /* The largest Legic Prime card is 1k */
+#define WRITE_LOWERLIMIT      4 /* UID and MCC are not writable */
+
+#define INPUT_THRESHOLD       8 /* heuristically determined, lower values */
+                                /* lead to detecting false ack during write */

 
 

+//-----------------------------------------------------------------------------
+// I/O interface abstraction (FPGA -> ARM)
+//-----------------------------------------------------------------------------
+
+static inline uint16_t rx_frame_from_fpga() {
+  for(;;) {
+    WDT_HIT();
+
+    // wait for frame be become available in rx holding register
+    if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
+      return AT91C_BASE_SSC->SSC_RHR;
+    }
+  }

 }
 
 }
 

-#define FUZZ_EQUAL(value, target, fuzz) ((value) > ((target)-(fuzz)) && (value) < ((target)+(fuzz)))
-
-static const struct legic_frame queries[] = {
-               {7, 0x55}, /* 1010 101 */
-};
-
-static const struct legic_frame responses[] = {
-               {6, 0x3b}, /* 1101 11 */
-};
-
-/* Send a frame in tag mode, the FPGA must have been set up by
- * LegicRfSimulate
- */
-static void frame_send_tag(uint16_t response, int bits)
-{
-#if 0
-       /* Use the SSC to send a response. 8-bit transfers, LSBit first, 100us per bit */
-#else 
-       /* Bitbang the response */
-       AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;
-       AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
-       AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
-       
-       /* Wait for the frame start */
-       while(timer->TC_CV < TAG_TIME_WAIT) ;
-       
-       int i;
-       for(i=0; i<bits; i++) {
-               int nextbit = timer->TC_CV + TAG_TIME_BIT;
-               int bit = response & 1;
-               response = response >> 1;
-               if(bit) 
-                       AT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT;
-               else
-                       AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;
-               while(timer->TC_CV < nextbit) ;
-       }
-       AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;
-#endif
+//-----------------------------------------------------------------------------
+// Demodulation (Reader)
+//-----------------------------------------------------------------------------
+
+// Returns a demedulated bit
+//
+// The FPGA running xcorrelation samples the subcarrier at ~13.56 MHz. The mode
+// was initialy designed to receive BSPK/2-PSK. Hance, it reports an I/Q pair
+// every 4.7us (8 bits i and 8 bits q).
+//
+// The subcarrier amplitude can be calculated using Pythagoras sqrt(i^2 + q^2).
+// To reduce CPU time the amplitude is approximated by using linear functions:
+//   am = MAX(ABS(i),ABS(q)) + 1/2*MIN(ABS(i),ABSq))
+//
+// The bit time is 99.1us (21 I/Q pairs). The receiver skips the first 5 samples
+// and averages the next (most stable) 8 samples. The final 8 samples are dropped
+// also.
+//
+// The demodulated should be alligned to the bit period by the caller. This is
+// done in rx_bit and rx_ack.
+static inline bool rx_bit() {
+  int32_t sum_cq = 0;
+  int32_t sum_ci = 0;
+
+  // skip first 5 I/Q pairs
+  for(size_t i = 0; i<5; ++i) {
+    (void)rx_frame_from_fpga();
+  }
+
+  // sample next 8 I/Q pairs
+  for(size_t i = 0; i<8; ++i) {
+    uint16_t iq = rx_frame_from_fpga();
+    int8_t ci = (int8_t)(iq >> 8);
+    int8_t cq = (int8_t)(iq & 0xff);
+    sum_ci += ci;
+    sum_cq += cq;
+  }
+
+  // calculate power
+  int32_t power = (MAX(ABS(sum_ci), ABS(sum_cq)) + MIN(ABS(sum_ci), ABS(sum_cq))/2);
+
+  // compare average (power / 8) to threshold
+  return ((power >> 3) > INPUT_THRESHOLD);

 }
 
 }
 

-/* Send a frame in reader mode, the FPGA must have been set up by
- * LegicRfReader
- */
-static void frame_send_rwd(uint16_t data, int bits)
-{
-       /* Start clock */
-       timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
-       while(timer->TC_CV > 1) ; /* Wait till the clock has reset */
-       
-       int i;
-       for(i=0; i<bits; i++) {
-               int starttime = timer->TC_CV;
-               int pause_end = starttime + RWD_TIME_PAUSE, bit_end;
-               int bit = data & 1;
-               data = data >> 1;
-               
-               if(bit) {
-                       bit_end = starttime + RWD_TIME_1;
-               } else {
-                       bit_end = starttime + RWD_TIME_0;
-               }
-               
-               /* RWD_TIME_PAUSE time off, then some time on, so that the complete bit time is
-                * RWD_TIME_x, where x is the bit to be transmitted */
-               AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;
-               while(timer->TC_CV < pause_end) ;
-               AT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT;
-               while(timer->TC_CV < bit_end) ;
-       }
-       
-       {
-               /* One final pause to mark the end of the frame */
-               int pause_end = timer->TC_CV + RWD_TIME_PAUSE;
-               AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;
-               while(timer->TC_CV < pause_end) ;
-               AT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT;
-       }
-       
-       /* Reset the timer, to measure time until the start of the tag frame */
-       timer->TC_CCR = AT91C_TC_SWTRG;
+//-----------------------------------------------------------------------------
+// Modulation (Reader)
+//
+// I've tried to modulate the Legic specific pause-puls using ssc and the default
+// ssc clock of 105.4 kHz (bit periode of 9.4us) - previous commit. However,
+// the timing was not precise enough. By increasing the ssc clock this could
+// be circumvented, but the adventage over bitbang would be little.
+//-----------------------------------------------------------------------------
+
+static inline void tx_bit(bool bit) {
+  // insert pause
+  HIGH(GPIO_SSC_DOUT);
+  last_frame_end += RWD_TIME_PAUSE;
+  while(GET_TICKS < last_frame_end) { };
+
+  // return to carrier on, wait for bit periode to end
+  LOW(GPIO_SSC_DOUT);
+  last_frame_end += (bit ? RWD_TIME_1 : RWD_TIME_0) - RWD_TIME_PAUSE;
+  while(GET_TICKS < last_frame_end) { };

 }
 
 }
 

-/* Receive a frame from the card in reader emulation mode, the FPGA and
- * timer must have been set up by LegicRfReader and frame_send_rwd.
- * 
- * The LEGIC RF protocol from card to reader does not include explicit
- * frame start/stop information or length information. The reader must
- * know beforehand how many bits it wants to receive. (Notably: a card
- * sending a stream of 0-bits is indistinguishable from no card present.)
- * 
- * Receive methodology: There is a fancy correlator in hi_read_rx_xcorr, but
- * I'm not smart enough to use it. Instead I have patched hi_read_tx to output
- * the ADC signal with hysteresis on SSP_DIN. Bit-bang that signal and look
- * for edges. Count the edges in each bit interval. If they are approximately
- * 0 this was a 0-bit, if they are approximately equal to the number of edges
- * expected for a 212kHz subcarrier, this was a 1-bit. For timing we use the
- * timer that's still running from frame_send_rwd in order to get a synchronization
- * with the frame that we just sent.
- * 
- * FIXME: Because we're relying on the hysteresis to just do the right thing 
- * the range is severely reduced (and you'll probably also need a good antenna).
- * So this should be fixed some time in the future for a proper receiver. 
- */
-static void frame_receive_rwd(struct legic_frame * const f, int bits)
-{
-       uint16_t the_bit = 1;  /* Use a bitmask to save on shifts */
-       uint16_t data=0;
-       int i, old_level=0, edges=0;
-       int next_bit_at = TAG_TIME_WAIT;
-       
-       
-       if(bits > 16)
-               bits = 16;
-
-       AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
-       AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
-
-       while(timer->TC_CV < next_bit_at) ;
-       next_bit_at += TAG_TIME_BIT;
-       
-       for(i=0; i<bits; i++) {
-               edges = 0;
-               while(timer->TC_CV < next_bit_at) {
-                       int level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
-                       if(level != old_level)
-                               edges++;
-                       old_level = level;
-               }
-               next_bit_at += TAG_TIME_BIT;
-               
-               if(edges > 20 && edges < 60) { /* expected are 42 edges */
-                       data |= the_bit;
-               }
-               
-               
-               the_bit <<= 1;
-       }
-       
-       f->data = data;
-       f->bits = bits;
+//-----------------------------------------------------------------------------
+// Frame Handling (Reader)
+//
+// The LEGIC RF protocol from card to reader does not include explicit frame
+// start/stop information or length information. The reader must know beforehand
+// how many bits it wants to receive.
+// Notably: a card sending a stream of 0-bits is indistinguishable from no card
+// present.
+//-----------------------------------------------------------------------------
+
+static void tx_frame(uint32_t frame, uint8_t len) {
+  FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER | FPGA_HF_READER_MODE_SEND_FULL_MOD);
+
+  // wait for next tx timeslot
+  last_frame_end += RWD_FRAME_WAIT;
+  while(GET_TICKS < last_frame_end) { };
+
+  // transmit frame, MSB first
+  for(uint8_t i = 0; i < len; ++i) {
+    bool bit = (frame >> i) & 0x01;
+    tx_bit(bit ^ legic_prng_get_bit());
+    legic_prng_forward(1);
+  };
+
+  // add pause to mark end of the frame
+  HIGH(GPIO_SSC_DOUT);
+  last_frame_end += RWD_TIME_PAUSE;
+  while(GET_TICKS < last_frame_end) { };
+  LOW(GPIO_SSC_DOUT);

 }
 
 }
 

-/* Figure out a response to a frame in tag mode */
-static void frame_respond_tag(struct legic_frame const * const f)
-{
-       LED_D_ON();
-       int i, r_size;
-       uint16_t r_data;
-       
-       for(i=0; i<sizeof(queries)/sizeof(queries[0]); i++) {
-               if(f->bits == queries[i].bits && f->data == queries[i].data) {
-                       r_data = responses[i].data;
-                       r_size = responses[i].bits;
-                       break;
-               }
-       }
-       
-       if(r_size != 0) {
-               frame_send_tag(r_data, r_size);
-               LED_A_ON();
-       } else {
-               LED_A_OFF();
-       }
-       
-       LED_D_OFF();
+static uint32_t rx_frame(uint8_t len) {
+  FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER | FPGA_HF_READER_SUBCARRIER_212_KHZ | FPGA_HF_READER_MODE_RECEIVE_IQ);
+
+  // hold sampling until card is expected to respond
+  last_frame_end += TAG_FRAME_WAIT;
+  while(GET_TICKS < last_frame_end) { };
+
+  uint32_t frame = 0;
+  for(uint8_t i = 0; i < len; ++i) {
+    frame |= (rx_bit() ^ legic_prng_get_bit()) << i;
+    legic_prng_forward(1);
+
+    // rx_bit runs only 95us, resync to TAG_BIT_PERIOD
+    last_frame_end += TAG_BIT_PERIOD;
+    while(GET_TICKS < last_frame_end) { };
+  }
+
+  return frame;

 }
 
 }
 

-static void frame_append_bit(struct legic_frame * const f, int bit)
-{
-       if(f->bits >= 15)
-               return; /* Overflow, won't happen */
-       f->data |= (bit<<f->bits);
-       f->bits++;
+static bool rx_ack() {
+  // change fpga into rx mode
+  FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER | FPGA_HF_READER_SUBCARRIER_212_KHZ | FPGA_HF_READER_MODE_RECEIVE_IQ);
+
+  // hold sampling until card is expected to respond
+  last_frame_end += TAG_FRAME_WAIT;
+  while(GET_TICKS < last_frame_end) { };
+
+  uint32_t ack = 0;
+  for(uint8_t i = 0; i < TAG_WRITE_TIMEOUT; ++i) {
+    // sample bit
+    ack = rx_bit();
+    legic_prng_forward(1);
+
+    // rx_bit runs only 95us, resync to TAG_BIT_PERIOD
+    last_frame_end += TAG_BIT_PERIOD;
+    while(GET_TICKS < last_frame_end) { };
+
+    // check if it was an ACK
+    if(ack) {
+      break;
+    }
+  }
+
+  return ack;

 }
 
 }
 

-static int frame_is_empty(struct legic_frame const * const f)
-{
-       return( f->bits <= 4 );
+//-----------------------------------------------------------------------------
+// Legic Reader
+//-----------------------------------------------------------------------------
+
+static int init_card(uint8_t cardtype, legic_card_select_t *p_card) {
+  p_card->tagtype = cardtype;
+
+  switch(p_card->tagtype) {
+    case 0x0d:
+      p_card->cmdsize = 6;
+      p_card->addrsize = 5;
+      p_card->cardsize = 22;
+      break;
+    case 0x1d:
+      p_card->cmdsize = 9;
+      p_card->addrsize = 8;
+      p_card->cardsize = 256;
+      break;
+    case 0x3d:
+      p_card->cmdsize = 11;
+      p_card->addrsize = 10;
+      p_card->cardsize = 1024;
+      break;
+    default:
+      p_card->cmdsize = 0;
+      p_card->addrsize = 0;
+      p_card->cardsize = 0;
+      return 2;
+  }
+  return 0;

 }
 
 }
 

-/* Handle (whether to respond) a frame in tag mode */
-static void frame_handle_tag(struct legic_frame const * const f)
-{
-       if(f->bits == 6) {
-               /* Short path */
-               return;
-       }
-       if( !frame_is_empty(f) ) {
-               frame_respond_tag(f);
-       }
+static void init_reader(bool clear_mem) {
+  // configure FPGA
+  FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
+  FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER | FPGA_HF_READER_SUBCARRIER_212_KHZ | FPGA_HF_READER_MODE_RECEIVE_IQ);
+  SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
+  LED_D_ON();
+
+  // configure SSC with defaults
+  FpgaSetupSsc(FPGA_MAJOR_MODE_HF_READER);
+
+  // re-claim GPIO_SSC_DOUT as GPIO and enable output
+  AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
+  AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
+  LOW(GPIO_SSC_DOUT);
+
+  // init crc calculator
+  crc_init(&legic_crc, 4, 0x19 >> 1, 0x05, 0);
+
+  // start us timer
+  StartTicks();

 }
 
 }
 

-static void frame_clean(struct legic_frame * const f)
-{
-       f->data = 0;
-       f->bits = 0;
+// Setup reader to card connection
+//
+// The setup consists of a three way handshake:
+//  - Transmit initialisation vector 7 bits
+//  - Receive card type 6 bits
+//  - Transmit Acknowledge 6 bits
+static uint32_t setup_phase(uint8_t iv) {
+  // init coordination timestamp
+  last_frame_end = GET_TICKS;
+
+  // Switch on carrier and let the card charge for 5ms.
+  last_frame_end += 7500;
+  while(GET_TICKS < last_frame_end) { };
+
+  legic_prng_init(0);
+  tx_frame(iv, 7);
+
+  // configure prng
+  legic_prng_init(iv);
+  legic_prng_forward(2);
+
+  // receive card type
+  int32_t card_type = rx_frame(6);
+  legic_prng_forward(3);
+
+  // send obsfuscated acknowledgment frame
+  switch (card_type) {
+    case 0x0D:
+      tx_frame(0x19, 6); // MIM22 | READCMD = 0x18 | 0x01
+      break;
+    case 0x1D:
+    case 0x3D:
+      tx_frame(0x39, 6); // MIM256 | READCMD = 0x38 | 0x01
+      break;
+  }
+
+  return card_type;

 }
 
 }
 

-enum emit_mode { 
-       EMIT_RWD, /* Emit in tag simulation mode, e.g. the source is the RWD */
-       EMIT_TAG  /* Emit in reader simulation mode, e.g. the source is the TAG */
-}; 
-static void emit(enum emit_mode mode, int bit)
-{
-       if(bit == -1) {
-               if(mode == EMIT_RWD) {
-                       frame_handle_tag(&current_frame);
-               }
-               frame_clean(&current_frame);
-       } else if(bit == 0) {
-               frame_append_bit(&current_frame, 0);
-       } else if(bit == 1) {
-               frame_append_bit(&current_frame, 1);
-       }
+static uint8_t calc_crc4(uint16_t cmd, uint8_t cmd_sz, uint8_t value) {
+  crc_clear(&legic_crc);
+  crc_update(&legic_crc, (value << cmd_sz) | cmd, 8 + cmd_sz);
+  return crc_finish(&legic_crc);

 }
 
 }
 

-void LegicRfSimulate(void)
-{
-       /* ADC path high-frequency peak detector, FPGA in high-frequency simulator mode, 
-        * modulation mode set to 212kHz subcarrier. We are getting the incoming raw
-        * envelope waveform on DIN and should send our response on DOUT.
-        * 
-        * The LEGIC RF protocol is pulse-pause-encoding from reader to card, so we'll
-        * measure the time between two rising edges on DIN, and no encoding on the
-        * subcarrier from card to reader, so we'll just shift out our verbatim data
-        * on DOUT, 1 bit is 100us. The time from reader to card frame is still unclear,
-        * seems to be 300us-ish.
-        */
-       SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
-       FpgaSetupSsc();
-       FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_212K);
-       
-       /* Bitbang the receiver */
-       AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
-       AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
-       
-       setup_timer();
-       
-       int old_level = 0;
-       int active = 0;
-       
-       while(!BUTTON_PRESS()) {
-               int level = !!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
-               int time = timer->TC_CV;
-               
-               if(level != old_level) {
-                       if(level == 1) {
-                               timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
-                               if(FUZZ_EQUAL(time, RWD_TIME_1, RWD_TIME_FUZZ)) {
-                                       /* 1 bit */
-                                       emit(EMIT_RWD, 1);
-                                       active = 1;
-                                       LED_B_ON();
-                               } else if(FUZZ_EQUAL(time, RWD_TIME_0, RWD_TIME_FUZZ)) {
-                                       /* 0 bit */
-                                       emit(EMIT_RWD, 0);
-                                       active = 1;
-                                       LED_B_ON();
-                               } else if(active) {
-                                       /* invalid */
-                                       emit(EMIT_RWD, -1);
-                                       active = 0;
-                                       LED_B_OFF();
-                               }
-                       }
-               }
-               
-               if(time >= (RWD_TIME_1+RWD_TIME_FUZZ) && active) {
-                       /* Frame end */
-                       emit(EMIT_RWD, -1);
-                       active = 0;
-                       LED_B_OFF();
-               }
-               
-               if(time >= (20*RWD_TIME_1) && (timer->TC_SR & AT91C_TC_CLKSTA)) {
-                       timer->TC_CCR = AT91C_TC_CLKDIS;
-               }
-               
-               
-               old_level = level;
-               WDT_HIT();
-       }
+static int16_t read_byte(uint16_t index, uint8_t cmd_sz) {
+  uint16_t cmd = (index << 1) | LEGIC_READ;
+
+  // read one byte
+  LED_B_ON();
+  legic_prng_forward(2);
+  tx_frame(cmd, cmd_sz);
+  legic_prng_forward(2);
+  uint32_t frame = rx_frame(12);
+  LED_B_OFF();
+
+  // split frame into data and crc
+  uint8_t byte = BYTEx(frame, 0);
+  uint8_t crc = BYTEx(frame, 1);
+
+  // check received against calculated crc
+  uint8_t calc_crc = calc_crc4(cmd, cmd_sz, byte);
+  if(calc_crc != crc) {
+    Dbprintf("!!! crc mismatch: %x != %x !!!",  calc_crc, crc);
+    return -1;
+  }
+
+  legic_prng_forward(1);
+
+  return byte;

 }
 
 }
 

-void LegicRfReader(void)
-{
-       SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
-       FpgaSetupSsc();
-       FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX);
-       
-       /* Bitbang the transmitter */
-       AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;
-       AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
-       AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
-       
-       setup_timer();
-       
-       while(!BUTTON_PRESS()) {
-               /* Switch on carrier and let the tag charge for 1ms */
-               AT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT;
-               SpinDelay(1);
-               
-               LED_A_ON();
-               frame_send_rwd(queries[0].data, queries[0].bits);
-               LED_A_OFF();
-               
-               frame_clean(&current_frame);
-               LED_B_ON();
-               frame_receive_rwd(&current_frame, responses[0].bits);
-               LED_B_OFF();
-               
-               /* Switch off carrier, make sure tag is reset */
-               AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;
-               SpinDelay(10);
-               
-               WDT_HIT();
-       }
-       
+// Transmit write command, wait until (3.6ms) the tag sends back an unencrypted
+// ACK ('1' bit) and forward the prng time based.
+bool write_byte(uint16_t index, uint8_t byte, uint8_t addr_sz) {
+  uint32_t cmd = index << 1 | LEGIC_WRITE;          // prepare command
+  uint8_t  crc = calc_crc4(cmd, addr_sz + 1, byte); // calculate crc
+  cmd |= byte << (addr_sz + 1);                     // append value
+  cmd |= (crc & 0xF) << (addr_sz + 1 + 8);          // and crc
+
+  // send write command
+  LED_C_ON();
+  legic_prng_forward(2);
+  tx_frame(cmd, addr_sz + 1 + 8 + 4); // sz = addr_sz + cmd + data + crc
+  legic_prng_forward(3);
+  LED_C_OFF();
+
+  // wait for ack
+  return rx_ack();
+}
+
+//-----------------------------------------------------------------------------
+// Command Line Interface
+//
+// Only this functions are public / called from appmain.c
+//-----------------------------------------------------------------------------
+void LegicRfReader(int offset, int bytes) {
+  uint8_t *BigBuf = BigBuf_get_addr();
+  memset(BigBuf, 0, 1024);
+
+  // configure ARM and FPGA
+  init_reader(false);
+
+  // establish shared secret and detect card type
+  DbpString("Reading card ...");
+  uint8_t card_type = setup_phase(SESSION_IV);
+  uint8_t result = 0;
+  if(init_card(card_type, &card) != 0) {
+    result = 1;
+    goto OUT;
+  }
+
+  // if no argument is specified create full dump
+  if(bytes == -1) {
+    bytes = card.cardsize;
+  }
+
+  // do not read beyond card memory
+  if(bytes + offset > card.cardsize) {
+    bytes = card.cardsize - offset;
+  }
+
+  for(uint16_t i = 0; i < bytes; ++i) {
+    int16_t byte = read_byte(offset + i, card.cmdsize);
+    if(byte == -1) {
+      result = 2;
+      goto OUT;
+    }
+    BigBuf[i] = byte;
+  }
+
+OUT:
+  cmd_send(CMD_ACK, result, bytes, 0, &card, sizeof(card));
+  FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+  LED_B_OFF();
+  LED_C_OFF();
+  LED_D_OFF();
+  StopTicks();
+}
+
+void LegicRfWriter(int bytes, int offset) {
+  uint8_t *BigBuf = BigBuf_get_addr();
+
+  // configure ARM and FPGA
+  init_reader(false);
+
+  // uid is not writeable
+  if(offset <= WRITE_LOWERLIMIT) {
+    goto OUT;
+  }
+
+  // establish shared secret and detect card type
+  Dbprintf("Writing 0x%02.2x - 0x%02.2x ...", offset, offset+bytes);
+  uint8_t card_type = setup_phase(SESSION_IV);
+  if(init_card(card_type, &card) != 0) {
+    Dbprintf("No or unknown card found, aborting");
+    goto OUT;
+  }
+
+  // do not write beyond card memory
+  if(bytes + offset > card.cardsize) {
+    bytes = card.cardsize - offset;
+  }
+
+  // write in reverse order, only then is DCF (decremental field) writable
+  while(bytes-- > 0 && !BUTTON_PRESS()) {
+    if(!write_byte(bytes + offset, BigBuf[bytes + offset], card.addrsize)) {
+      Dbprintf("operation failed @ 0x%03.3x", bytes);
+      goto OUT;
+    }
+  }
+
+  // OK
+  DbpString("Write successful");
+
+OUT:
+  FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+  LED_B_OFF();
+  LED_C_OFF();
+  LED_D_OFF();
+  StopTicks();

 }
 }