Fix up small error in main osc startup delay and replace more custom defines with...

[proxmark3-svn] / bootrom / bootrom.c

diff --git a/bootrom/bootrom.c b/bootrom/bootrom.c
index da0de9c72190c28e3f70e866712a4bbde2caf493..6b0ff532800be0129b364d9413c22f3fdf84001b 100644 (file)
--- a/bootrom/bootrom.c
+++ b/bootrom/bootrom.c
@@ -1,3 +1,11 @@
+//-----------------------------------------------------------------------------
+// This code is licensed to you under the terms of the GNU GPL, version 2 or,
+// at your option, any later version. See the LICENSE.txt file for the text of
+// the license.
+//-----------------------------------------------------------------------------
+// Main code for the bootloader
+//-----------------------------------------------------------------------------
+
 #include <proxmark3.h>
 
 struct common_area common_area __attribute__((section(".commonarea")));
@@ -21,21 +29,22 @@ static void ConfigClocks(void)
                (1<<AT91C_ID_PWMC)      |
                (1<<AT91C_ID_UDP);
 
-       // worst case scenario, with 16Mhz xtal startup delay is 14.5ms
-       // with a slow clock running at it worst case (max) frequency of 42khz
-       // max startup delay = (14.5ms*42k)/8 = 76 = 0x4C round up to 0x50
+       // worst case scenario, with MAINCK = 16Mhz xtal, startup delay is 1.4ms
+       // if SLCK slow clock runs at its worst case (max) frequency of 42khz
+       // max startup delay = (1.4ms*42k)/8 = 7.356 so round up to 8
 
        // enable main oscillator and set startup delay
     AT91C_BASE_PMC->PMC_MOR =
-       PMC_MAIN_OSC_ENABLE |
-        PMC_MAIN_OSC_STARTUP_DELAY(0x50);
+        AT91C_CKGR_MOSCEN |
+        PMC_MAIN_OSC_STARTUP_DELAY(8);
 
        // wait for main oscillator to stabilize
-       while ( !(AT91C_BASE_PMC->PMC_SR & PMC_MAIN_OSC_STABILIZED) )
+       while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS) )
                ;
 
-    // minimum PLL clock frequency is 80 MHz in range 00 (96 here so okay)
-    // frequency is crystal * multiplier / divisor = 16Mhz * 12 / 2 = 96Mhz
+    // PLL output clock frequency in range  80 - 160 MHz needs CKGR_PLL = 00
+    // PLL output clock frequency in range 150 - 180 MHz needs CKGR_PLL = 10
+    // PLL output is MAINCK * multiplier / divisor = 16Mhz * 12 / 2 = 96Mhz
     AT91C_BASE_PMC->PMC_PLLR =
        PMC_PLL_DIVISOR(2) |
                PMC_PLL_COUNT_BEFORE_LOCK(0x50) |
@@ -44,23 +53,23 @@ static void ConfigClocks(void)
                PMC_PLL_USB_DIVISOR(1);
 
        // wait for PLL to lock
-       while ( !(AT91C_BASE_PMC->PMC_SR & PMC_MAIN_OSC_PLL_LOCK) )
+       while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK) )
                ;
 
        // we want a master clock (MCK) to be PLL clock / 2 = 96Mhz / 2 = 48Mhz
-       // as per datasheet, this register must be programmed in two operations
+       // datasheet recommends that this register is programmed in two operations
        // when changing to PLL, program the prescaler first then the source
-    AT91C_BASE_PMC->PMC_MCKR = PMC_CLK_PRESCALE_DIV_2;
+    AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
 
        // wait for main clock ready signal
-       while ( !(AT91C_BASE_PMC->PMC_SR & PMC_MAIN_OSC_MCK_READY) )
+       while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) )
                ;
 
        // set the source to PLL
-    AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | PMC_CLK_PRESCALE_DIV_2;
+    AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 | AT91C_PMC_CSS_PLL_CLK;
 
        // wait for main clock ready signal
-       while ( !(AT91C_BASE_PMC->PMC_SR & PMC_MAIN_OSC_MCK_READY) )
+       while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) )
                ;
 }
 
@@ -69,11 +78,11 @@ static void Fatal(void)
     for(;;);
 }
 
-void UsbPacketReceived(BYTE *packet, int len)
+void UsbPacketReceived(uint8_t *packet, int len)
 {
     int i, dont_ack=0;
     UsbCommand *c = (UsbCommand *)packet;
-    volatile DWORD *p;
+    volatile uint32_t *p;
 
     if(len != sizeof(*c)) {
         Fatal();
@@ -93,14 +102,14 @@ void UsbPacketReceived(BYTE *packet, int len)
             /* The temporary write buffer of the embedded flash controller is mapped to the
              * whole memory region, only the last 8 bits are decoded.
              */
-            p = (volatile DWORD *)&_flash_start;
+            p = (volatile uint32_t *)&_flash_start;
             for(i = 0; i < 12; i++) {
                 p[i+c->arg[0]] = c->d.asDwords[i];
             }
             break;
 
         case CMD_FINISH_WRITE:
-            p = (volatile DWORD *)&_flash_start;
+            p = (volatile uint32_t *)&_flash_start;
             for(i = 0; i < 4; i++) {
                 p[i+60] = c->d.asDwords[i];
             }
@@ -120,9 +129,9 @@ void UsbPacketReceived(BYTE *packet, int len)
 
             uint32_t sr;
 
-            while(!((sr = AT91C_BASE_EFC0->EFC_FSR) & MC_FLASH_STATUS_READY))
+            while(!((sr = AT91C_BASE_EFC0->EFC_FSR) & AT91C_MC_FRDY))
                 ;
-            if(sr & (MC_FLASH_STATUS_LOCKE | MC_FLASH_STATUS_PROGE)) {
+            if(sr & (AT91C_MC_LOCKE | AT91C_MC_PROGE)) {
                    dont_ack = 1;
                     c->cmd = CMD_NACK;
                     UsbSendPacket(packet, len);
@@ -248,19 +257,9 @@ void BootROM(void)
     LED_B_OFF();
     LED_A_OFF();
 
-    // if 512K FLASH part - TODO make some defines :)
-    if ((AT91C_BASE_DBGU->DBGU_CIDR | 0xf00) == 0xa00) {
-           AT91C_BASE_EFC0->EFC_FMR =
-               MC_FLASH_MODE_FLASH_WAIT_STATES(1) |
-                       MC_FLASH_MODE_MASTER_CLK_IN_MHZ(0x48);
-           AT91C_BASE_EFC1->EFC_FMR =
-               MC_FLASH_MODE_FLASH_WAIT_STATES(1) |
-                       MC_FLASH_MODE_MASTER_CLK_IN_MHZ(0x48);
-    } else {
-           AT91C_BASE_EFC0->EFC_FMR =
-               MC_FLASH_MODE_FLASH_WAIT_STATES(0) |
-                       MC_FLASH_MODE_MASTER_CLK_IN_MHZ(48);
-    }
+       AT91C_BASE_EFC0->EFC_FMR =
+               AT91C_MC_FWS_1FWS |
+               MC_FLASH_MODE_MASTER_CLK_IN_MHZ(48);
 
     // Initialize all system clocks
     ConfigClocks();