X-Git-Url: http://git.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/5ea2a24839c71ba6e58af937a392a6204b8b4696..1963cc9fe0ab7d6ddd04c5f8b4f27af836e98335:/fpga/hi_simulate.v

diff --git a/fpga/hi_simulate.v b/fpga/hi_simulate.v
index de58a74e..097b8a08 100644
--- a/fpga/hi_simulate.v
+++ b/fpga/hi_simulate.v
@@ -33,60 +33,80 @@ module hi_simulate(
     output dbg;
     input [2:0] mod_type;
 
+assign adc_clk = ck_1356meg;
 
 // The comparator with hysteresis on the output from the peak detector.
 reg after_hysteresis;
-assign adc_clk = ck_1356meg;
+reg [11:0] has_been_low_for;
 
 always @(negedge adc_clk)
 begin
-    if(& adc_d[7:5]) after_hysteresis = 1'b1;           // if (adc_d >= 224)
-    else if(~(| adc_d[7:5])) after_hysteresis = 1'b0;   // if (adc_d <= 31)
+    if (& adc_d[7:5]) after_hysteresis <= 1'b1;           // if (adc_d >= 224)
+    else if (~(| adc_d[7:5])) after_hysteresis <= 1'b0;   // if (adc_d <= 31)
+
+	if (adc_d >= 224)
+    begin
+        has_been_low_for <= 12'd0;
+    end
+    else
+    begin
+        if (has_been_low_for == 12'd4095)
+        begin
+            has_been_low_for <= 12'd0;
+            after_hysteresis <= 1'b1;
+        end
+        else
+		begin
+            has_been_low_for <= has_been_low_for + 1;
+		end	
+    end
 end
 
 
 // Divide 13.56 MHz to produce various frequencies for SSP_CLK
 // and modulation.
-reg [7:0] ssp_clk_divider;
+reg [8:0] ssp_clk_divider;
 
-always @(posedge adc_clk)
+always @(negedge adc_clk)
     ssp_clk_divider <= (ssp_clk_divider + 1);
 
 reg ssp_clk;
 
 always @(negedge adc_clk)
 begin
-    if(mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K_8BIT)
+    if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K_8BIT)
       // Get bit every at 53KHz (every 8th carrier bit of 424kHz)
-      ssp_clk <= ssp_clk_divider[7];
-    else if(mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K)
+      ssp_clk <= ~ssp_clk_divider[7];
+    else if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K)
       // Get next bit at 212kHz
-      ssp_clk <= ssp_clk_divider[5];
+      ssp_clk <= ~ssp_clk_divider[5];
     else
       // Get next bit at 424Khz
-      ssp_clk <= ssp_clk_divider[4];
+      ssp_clk <= ~ssp_clk_divider[4];
 end
 
 
-// Divide SSP_CLK by 8 to produce the byte framing signal; the phase of
-// this is arbitrary, because it's just a bitstream.
-// One nasty issue, though: I can't make it work with both rx and tx at
-// once. The phase wrt ssp_clk must be changed. TODO to find out why
-// that is and make a better fix.
-reg [2:0] ssp_frame_divider_to_arm;
-always @(posedge ssp_clk)
-    ssp_frame_divider_to_arm <= (ssp_frame_divider_to_arm + 1);
-reg [2:0] ssp_frame_divider_from_arm;
-always @(negedge ssp_clk)
-    ssp_frame_divider_from_arm <= (ssp_frame_divider_from_arm + 1);
-
-
+// Produce the byte framing signal; the phase of this signal 
+// is arbitrary, because it's just a bit stream in this module.
 reg ssp_frame;
-always @(ssp_frame_divider_to_arm or ssp_frame_divider_from_arm or mod_type)
-    if(mod_type == `FPGA_HF_SIMULATOR_NO_MODULATION) // not modulating, so listening, to ARM
-        ssp_frame = (ssp_frame_divider_to_arm == 3'b000);
-    else
-        ssp_frame = (ssp_frame_divider_from_arm == 3'b000);
+always @(negedge adc_clk)
+begin
+	if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K)
+	begin
+		if (ssp_clk_divider[8:5] == 4'd1)
+			ssp_frame <= 1'b1;
+		if (ssp_clk_divider[8:5] == 4'd5)
+			ssp_frame <= 1'b0;
+	end
+	else
+	begin
+		if (ssp_clk_divider[7:4] == 4'd1)
+			ssp_frame <= 1'b1;
+		if (ssp_clk_divider[7:4] == 4'd5)
+			ssp_frame <= 1'b0;
+	end
+end
+
 
 // Synchronize up the after-hysteresis signal, to produce DIN.
 reg ssp_din;
@@ -120,6 +140,6 @@ assign pwr_lo = 1'b0;
 assign pwr_oe2 = 1'b0;
 
 
-assign dbg = ssp_din;
+assign dbg = ssp_frame;
 
 endmodule