X-Git-Url: http://git.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/b811cc51f9a21324dc7589d1254e767374488a20..6658905f18a1eebc148836f26c731dea9c1377dc:/fpga/fpga.ucf

diff --git a/fpga/fpga.ucf b/fpga/fpga.ucf
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+# See the schematic for the pin assignment.
+
+NET "adc_d<0>"  LOC = "P62"  ; 
+NET "adc_d<1>"  LOC = "P60"  ; 
+NET "adc_d<2>"  LOC = "P58"  ; 
+NET "adc_d<3>"  LOC = "P57"  ; 
+NET "adc_d<4>"  LOC = "P56"  ; 
+NET "adc_d<5>"  LOC = "P55"  ; 
+NET "adc_d<6>"  LOC = "P54"  ; 
+NET "adc_d<7>"  LOC = "P53"  ; 
+#NET "cross_hi"  LOC = "P88"  ; 
+#NET "miso"  LOC = "P40"  ; 
+#PACE: Start of Constraints generated by PACE
+
+#PACE: Start of PACE I/O Pin Assignments
+NET "adc_clk"  LOC = "P46"  ; 
+NET "adc_noe"  LOC = "P47"  ; 
+NET "ck_1356meg"  LOC = "P91"  ; 
+NET "ck_1356megb"  LOC = "P93"  ; 
+NET "cross_lo"  LOC = "P87"  ; 
+NET "dbg"  LOC = "P22"  ; 
+NET "mosi"  LOC = "P43"  ; 
+NET "ncs"  LOC = "P44"  ; 
+NET "pck0"  LOC = "P36"  ; 
+NET "pwr_hi"  LOC = "P80"  ; 
+NET "pwr_lo"  LOC = "P81"  ; 
+NET "pwr_oe1"  LOC = "P82"  ; 
+NET "pwr_oe2"  LOC = "P83"  ; 
+NET "pwr_oe3"  LOC = "P84"  ; 
+NET "pwr_oe4"  LOC = "P86"  ; 
+NET "spck"  LOC = "P39"  ; 
+NET "ssp_clk"  LOC = "P71"  ; 
+NET "ssp_din"  LOC = "P32"  ; 
+NET "ssp_dout"  LOC = "P34"  ; 
+NET "ssp_frame"  LOC = "P31"  ; 
+
+#PACE: Start of PACE Area Constraints
+
+#PACE: Start of PACE Prohibit Constraints
+
+#PACE: End of Constraints generated by PACE