X-Git-Url: http://git.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/c3adc9fd605d1bbed182314eec7a9b81891a789b..d3ae0de746962dfde04133fc2fdb8e9f6544771a:/armsrc/fpgaloader.c

diff --git a/armsrc/fpgaloader.c b/armsrc/fpgaloader.c
index 8cea61b0..af2f02ab 100644
--- a/armsrc/fpgaloader.c
+++ b/armsrc/fpgaloader.c
@@ -152,28 +152,50 @@ static void DownloadFPGA_byte(unsigned char w)
 // If bytereversal is set: reverse the byte order in each 4-byte word
 static void DownloadFPGA(const char *FpgaImage, int FpgaImageLen, int bytereversal)
 {
-	int i;
+	int i=0;
 
 	PIO_OUTPUT_ENABLE = (1 << GPIO_FPGA_ON);
 	PIO_ENABLE = (1 << GPIO_FPGA_ON);
-	PIO_OUTPUT_DATA_SET = (1 << GPIO_FPGA_ON);
+	HIGH(GPIO_FPGA_ON);		// ensure everything is powered on
 
 	SpinDelay(50);
 
 	LED_D_ON();
 
+	// These pins are inputs
+    PIO_OUTPUT_DISABLE =     (1 << GPIO_FPGA_NINIT) | (1 << GPIO_FPGA_DONE);
+	// PIO controls the following pins
+    PIO_ENABLE =             (1 << GPIO_FPGA_NINIT) | (1 << GPIO_FPGA_DONE);
+	// Enable pull-ups
+	PIO_NO_PULL_UP_DISABLE = (1 << GPIO_FPGA_NINIT) | (1 << GPIO_FPGA_DONE);
+
+	// setup initial logic state
 	HIGH(GPIO_FPGA_NPROGRAM);
 	LOW(GPIO_FPGA_CCLK);
 	LOW(GPIO_FPGA_DIN);
+	// These pins are outputs
 	PIO_OUTPUT_ENABLE = (1 << GPIO_FPGA_NPROGRAM)	|
 						(1 << GPIO_FPGA_CCLK)		|
 						(1 << GPIO_FPGA_DIN);
-	SpinDelay(1);
 
+	// enter FPGA configuration mode
 	LOW(GPIO_FPGA_NPROGRAM);
 	SpinDelay(50);
 	HIGH(GPIO_FPGA_NPROGRAM);
 
+	i=100000;
+	// wait for FPGA ready to accept data signal
+	while ((i) && ( !(PIO_PIN_DATA_STATUS & (1<<GPIO_FPGA_NINIT) ) ) ) {
+		i--;
+	}
+
+	// crude error indicator, leave both red LEDs on and return
+	if (i==0){
+		LED_C_ON();
+		LED_D_ON();
+		return;
+	}
+
 	if(bytereversal) {
 		/* This is only supported for DWORD aligned images */
 		if( ((int)FpgaImage % sizeof(DWORD)) == 0 ) {
@@ -183,7 +205,7 @@ static void DownloadFPGA(const char *FpgaImage, int FpgaImageLen, int byterevers
 			/* Explanation of the magic in the above line: 
 			 * i^0x3 inverts the lower two bits of the integer i, counting backwards
 			 * for each 4 byte increment. The generated sequence of (i++)^3 is
-			 * 3 2 1 0 7 6 5 4 11 10 9 8 15 14 13 12 etc. pp. 
+			 * 3 2 1 0 7 6 5 4 11 10 9 8 15 14 13 12 etc. pp. 
 			 */
 		}
 	} else {
@@ -191,6 +213,18 @@ static void DownloadFPGA(const char *FpgaImage, int FpgaImageLen, int byterevers
 			DownloadFPGA_byte(*FpgaImage++);
 	}
 
+	// continue to clock FPGA until ready signal goes high
+	i=100000;
+	while ( (i--) && ( !(PIO_PIN_DATA_STATUS & (1<<GPIO_FPGA_DONE) ) ) ) {
+		HIGH(GPIO_FPGA_CCLK);
+		LOW(GPIO_FPGA_CCLK);
+	}
+	// crude error indicator, leave both red LEDs on and return
+	if (i==0){
+		LED_C_ON();
+		LED_D_ON();
+		return;
+	}
 	LED_D_OFF();
 }