From: henryk@ploetzli.ch <henryk@ploetzli.ch@ef4ab9da-24cd-11de-8aaa-f3a34680c41f>
Date: Fri, 6 Nov 2009 15:36:57 +0000 (+0000)
Subject: Jerry-rig a simply hysteresis based receiver into hi_read_tx. Output is via SSC_DIN... 
X-Git-Tag: v1.0.0~455
X-Git-Url: http://git.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/commitdiff_plain/24fe4dffb49ca5c50983c54f1b1d51028c06390d

Jerry-rig a simply hysteresis based receiver into hi_read_tx. Output is via SSC_DIN, which wasn't used in that mode before.
---

diff --git a/fpga/fpga.bit b/fpga/fpga.bit
index a9b03e13..5e8ca76b 100644
Binary files a/fpga/fpga.bit and b/fpga/fpga.bit differ
diff --git a/fpga/hi_read_tx.v b/fpga/hi_read_tx.v
index c2cec3ab..5ddc974d 100644
--- a/fpga/hi_read_tx.v
+++ b/fpga/hi_read_tx.v
@@ -68,9 +68,22 @@ always @(negedge ssp_clk)
 
 assign ssp_frame = (hi_byte_div == 3'b000);
 
-assign ssp_din = 1'b0;
+// Implement a hysteresis to give out the received signal on
+// ssp_din. Sample at fc.
+assign adc_clk = ck_1356meg;
+
+// ADC data appears on the rising edge, so sample it on the falling edge
+reg after_hysteresis;
+always @(negedge adc_clk)
+begin
+    if(& adc_d[7:0]) after_hysteresis <= 1'b1;
+    else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;
+end
+
+
+assign ssp_din = after_hysteresis;
 
 assign pwr_lo = 1'b0;
-assign dbg = ssp_frame;
+assign dbg = ssp_din;
 
 endmodule