From 06b58a94f0be3256853a97387fc7e5782ce335c7 Mon Sep 17 00:00:00 2001 From: iceman1001 Date: Thu, 27 Nov 2014 22:16:17 +0100 Subject: [PATCH] BUG: don't try to fix things that ain't broken.. or not. My try for a fix ended up making the PrintAndLog function stop working. Just by calling a fclose.. fixed. --- armsrc/appmain.c | 1 + armsrc/lfops.c | 62 +++++++++++++++++++++------------------------- client/cmdlfem4x.c | 13 +++------- client/scripting.c | 4 +-- client/ui.c | 1 - 5 files changed, 35 insertions(+), 46 deletions(-) diff --git a/armsrc/appmain.c b/armsrc/appmain.c index 09acf41f..18c65e80 100644 --- a/armsrc/appmain.c +++ b/armsrc/appmain.c @@ -674,6 +674,7 @@ void UsbPacketReceived(uint8_t *packet, int len) case CMD_SIMULATE_TAG_125K: LED_A_ON(); SimulateTagLowFrequency(c->arg[0], c->arg[1], 0); + FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); LED_A_OFF(); break; case CMD_LF_SIMULATE_BIDIR: diff --git a/armsrc/lfops.c b/armsrc/lfops.c index 1a7c3224..0755e1e5 100644 --- a/armsrc/lfops.c +++ b/armsrc/lfops.c @@ -449,6 +449,12 @@ void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc) DbpString("Now use tiread to check"); } + + +// PIO_CODR = Clear Output Data Register +// PIO_SODR = Set Output Data Register +//#define LOW(x) AT91C_BASE_PIOA->PIO_CODR = (x) +//#define HIGH(x) AT91C_BASE_PIOA->PIO_SODR = (x) void SimulateTagLowFrequency(int period, int gap, int ledcontrol) { int i = 0; @@ -456,76 +462,64 @@ void SimulateTagLowFrequency(int period, int gap, int ledcontrol) FpgaDownloadAndGo(FPGA_BITSTREAM_LF); FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz - //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT); - FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU); + FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT); // Connect the A/D to the peak-detected low-frequency path. - //SetAdcMuxFor(GPIO_MUXSEL_LOPKD); - - // Configure output and enable pin that is connected to the FPGA (for modulating) - AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK; - AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT; // (PIO_PER) PIO Enable Register , - AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT; // (PIO_OER) Output Enable Register - AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK; // (PIO_ODR) Output Disable Register + SetAdcMuxFor(GPIO_MUXSEL_LOPKD); - // Give it a bit of time for the resonant antenna to settle. - SpinDelay(150); + // Now set up the SSC to get the ADC samples that are now streaming at us. + FpgaSetupSsc(); - while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); // wait for ssp_clk to go high - while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK); // wait for ssp_clk to go low + // Configure output and enable pin that is connected to the FPGA (for modulating) + // AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK; // (PIO_PER) PIO Enable Register + // AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT; // (PIO_OER) Output Enable Register + // AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK; // (PIO_ODR) Output Disable Register + + AT91C_BASE_PIOA->PIO_OER = GPIO_PCK0; while(!BUTTON_PRESS()) { WDT_HIT(); // PIO_PDSR = Pin Data Status Register // GPIO_SSC_CLK = SSC Transmit Clock - while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) { // wait for ssp_clk to go high + // wait ssp_clk == high + while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) { if(BUTTON_PRESS()) { DbpString("Stopped at 0"); - FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off return; } WDT_HIT(); } - - // PIO_CODR = Clear Output Data Register - // PIO_SODR = Set Output Data Register - //#define LOW(x) AT91C_BASE_PIOA->PIO_CODR = (x) - //#define HIGH(x) AT91C_BASE_PIOA->PIO_SODR = (x) if ( buf[i] > 0 ){ - HIGH(GPIO_SSC_DOUT); - //FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz - //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU); + OPEN_COIL(); } else { - LOW(GPIO_SSC_DOUT); - //FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); + SHORT_COIL(); } - while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) { // wait for ssp_clk to go low + DbpString("Enter Sim3"); + // wait ssp_clk == low + while( (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) ) { if(BUTTON_PRESS()) { - DbpString("Stopped at 1"); - FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off + DbpString("stopped at 1"); return; } WDT_HIT(); - } + } + DbpString("Enter Sim4 "); //SpinDelayUs(512); ++i; if(i == period) { i = 0; if (gap) { - // turn of modulation - LOW(GPIO_SSC_DOUT); - // wait - SpinDelay(gap); + SHORT_COIL(); + SpinDelay(gap); } } } DbpString("Stopped"); - FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); return; } diff --git a/client/cmdlfem4x.c b/client/cmdlfem4x.c index 07f909ac..8c6461df 100644 --- a/client/cmdlfem4x.c +++ b/client/cmdlfem4x.c @@ -196,7 +196,7 @@ retest: */ int CmdEM410xSim(const char *Cmd) { - int i, n, j, h, binary[4], parity[4]; + int i, n, j, binary[4], parity[4]; char cmdp = param_getchar(Cmd, 0); uint8_t uid[5] = {0x00}; @@ -222,9 +222,6 @@ int CmdEM410xSim(const char *Cmd) /* clear our graph */ ClearGraph(0); - /* write it out a few times */ - //for (h = 0; h < 4; h++) - //{ /* write 9 start bits */ for (i = 0; i < 9; i++) AppendGraph(0, clock, 1); @@ -260,11 +257,9 @@ int CmdEM410xSim(const char *Cmd) AppendGraph(0, clock, parity[2]); AppendGraph(0, clock, parity[3]); - /* stop bit */ - AppendGraph(0, clock, 0); - //} - - /* modulate that biatch */ + /* stop bit */ + AppendGraph(0, clock, 0); + //CmdManchesterMod("64"); /* booyah! */ diff --git a/client/scripting.c b/client/scripting.c index f0c56baf..cc59f995 100644 --- a/client/scripting.c +++ b/client/scripting.c @@ -268,8 +268,8 @@ static int l_crc16(lua_State *L) { size_t size; const char *p_str = luaL_checklstring(L, 1, &size); - - unsigned short retval = crc16_ccitt( p_str, size); + + uint16_t retval = crc16_ccitt( (uint8_t*) p_str, size); lua_pushinteger(L, (int) retval); return 1; } diff --git a/client/ui.c b/client/ui.c index d4758525..5111e295 100644 --- a/client/ui.c +++ b/client/ui.c @@ -79,7 +79,6 @@ void PrintAndLog(char *fmt, ...) vfprintf(logfile, fmt, argptr2); fprintf(logfile,"\n"); fflush(logfile); - fclose(logfile); // ICEMAN, this logfile is never closed?!? } va_end(argptr2); -- 2.39.2