From aae8787c039b0f8c87a34877c92297e8b7a89914 Mon Sep 17 00:00:00 2001 From: "henryk@ploetzli.ch" Date: Fri, 28 Aug 2009 21:53:54 +0000 Subject: [PATCH] Add defines for the timer/counter peripheral --- include/at91sam7s128.h | 168 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 168 insertions(+) diff --git a/include/at91sam7s128.h b/include/at91sam7s128.h index 7e7b3506..1142b209 100644 --- a/include/at91sam7s128.h +++ b/include/at91sam7s128.h @@ -460,4 +460,172 @@ #define PDC_TX_ENABLE (1<<8) #define PDC_TX_DISABLE (1<<9) +//------------- +// Timer/Counter base + +#define TC_BASE (0xfffa0000) + +#define TC_BCR REG(TC_BASE+0xC0) +#define TC_BMR REG(TC_BASE+0xC4) + +#define TC_BCR_SYNC (1<<0) + +#define TC_CCR_CLKEN (1<<0) +#define TC_CCR_CLKDIS (1<<1) +#define TC_CCR_SWTRG (1<<2) + +#define TC_CMR_TCCLKS (7<<0) +#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0<<0) +#define TC_CMR_TCCLKS_TIMER_CLOCK2 (1<<0) +#define TC_CMR_TCCLKS_TIMER_CLOCK3 (2<<0) +#define TC_CMR_TCCLKS_TIMER_CLOCK4 (3<<0) +#define TC_CMR_TCCLKS_TIMER_CLOCK5 (4<<0) +#define TC_CMR_TCCLKS_XC0 (5<<0) +#define TC_CMR_TCCLKS_XC1 (6<<0) +#define TC_CMR_TCCLKS_XC2 (7<<0) +#define TC_CMR_CLKI (1<<3) +#define TC_CMR_BURST (3<<4) +#define TC_CMR_BURST_XC0 (1<<4) +#define TC_CMR_BURST_XC1 (2<<4) +#define TC_CMR_BURST_XC2 (3<<4) +#define TC_CMR_LDBSTOP (1<<6) +#define TC_CMR_CPCSTOP (1<<6) +#define TC_CMR_LDBDIS (1<<7) +#define TC_CMR_CPCDIS (1<<7) +#define TC_CMR_ETRGEDG (3<<8) +#define TC_CMR_ETRGEDG_NONE (0<<8) +#define TC_CMR_ETRGEDG_RISING (1<<8) +#define TC_CMR_ETRGEDG_FALLING (2<<8) +#define TC_CMR_ETRGEDG_EACH (3<<8) +#define TC_CMR_EEVTEDG (3<<8) +#define TC_CMR_EEVTEDG_NONE (0<<8) +#define TC_CMR_EEVTEDG_RISING (1<<8) +#define TC_CMR_EEVTEDG_FALLING (2<<8) +#define TC_CMR_EEVTEDG_EACH (3<<8) +#define TC_CMR_ABETRG (1<<10) +#define TC_CMR_EEVT (3<<10) +#define TC_CMR_EEVT_TIOB (0<<10) +#define TC_CMR_EEVT_XC0 (1<<10) +#define TC_CMR_EEVT_XC1 (2<<10) +#define TC_CMR_EEVT_XC2 (3<<10) +#define TC_CMR_ENETRG (1<<12) +#define TC_CMR_WAVSEL (3<<13) +#define TC_CMR_WAVSEL_UP (0<<13) +#define TC_CMR_WAVSEL_UP_AUTO (2<<13) +#define TC_CMR_WAVSEL_UPDOWN (1<<13) +#define TC_CMR_WAVSEL_UPDOWN_AUTO (3<<13) +#define TC_CMR_CPCTRG (1<<14) +#define TC_CMR_WAVE (1<<15) +#define TC_CMR_LDRA (3<<16) +#define TC_CMR_LDRA_NONE (0<<16) +#define TC_CMR_LDRA_RISING (1<<16) +#define TC_CMR_LDRA_FALLING (2<<16) +#define TC_CMR_LDRA_EACH (3<<16) +#define TC_CMR_ACPA (3<<16) +#define TC_CMR_ACPA_NONE (0<<16) +#define TC_CMR_ACPA_SET (1<<16) +#define TC_CMR_ACPA_CLEAR (2<<16) +#define TC_CMR_ACPA_TOGGLE (3<<16) +#define TC_CMR_LDRB (3<<18) +#define TC_CMR_LDRB_NONE (0<<18) +#define TC_CMR_LDRB_RISING (1<<18) +#define TC_CMR_LDRB_FALLING (2<<18) +#define TC_CMR_LDRB_EACH (3<<18) +#define TC_CMR_ACPC (3<<18) +#define TC_CMR_ACPC_NONE (0<<18) +#define TC_CMR_ACPC_SET (1<<18) +#define TC_CMR_ACPC_CLEAR (2<<18) +#define TC_CMR_ACPC_TOGGLE (3<<18) +#define TC_CMR_AEEVT (3<<20) +#define TC_CMR_AEEVT_NONE (0<<20) +#define TC_CMR_AEEVT_SET (1<<20) +#define TC_CMR_AEEVT_CLEAR (2<<20) +#define TC_CMR_AEEVT_TOGGLE (3<<20) +#define TC_CMR_ASWTRG (3<<22) +#define TC_CMR_ASWTRG_NONE (0<<22) +#define TC_CMR_ASWTRG_SET (1<<22) +#define TC_CMR_ASWTRG_CLEAR (2<<22) +#define TC_CMR_ASWTRG_TOGGLE (3<<22) +#define TC_CMR_BCPB (3<<24) +#define TC_CMR_BCPB_NONE (0<<24) +#define TC_CMR_BCPB_SET (1<<24) +#define TC_CMR_BCPB_CLEAR (2<<24) +#define TC_CMR_BCPB_TOGGLE (3<<24) +#define TC_CMR_BCPC (3<<26) +#define TC_CMR_BCPC_NONE (0<<26) +#define TC_CMR_BCPC_SET (1<<26) +#define TC_CMR_BCPC_CLEAR (2<<26) +#define TC_CMR_BCPC_TOGGLE (3<<26) +#define TC_CMR_BEEVT (3<<28) +#define TC_CMR_BEEVT_NONE (0<<28) +#define TC_CMR_BEEVT_SET (1<<28) +#define TC_CMR_BEEVT_CLEAR (2<<28) +#define TC_CMR_BEEVT_TOGGLE (3<<28) +#define TC_CMR_BSWTRG (3<<30) +#define TC_CMR_BSWTRG_NONE (0<<30) +#define TC_CMR_BSWTRG_SET (1<<30) +#define TC_CMR_BSWTRG_CLEAR (2<<30) +#define TC_CMR_BSWTRG_TOGGLE (3<<30) + +#define TC_SR_COVFS (1<<0) +#define TC_SR_LOVFS (1<<1) +#define TC_SR_CPAS (1<<2) +#define TC_SR_CPBS (1<<3) +#define TC_SR_CPCS (1<<4) +#define TC_SR_LDRAS (1<<5) +#define TC_SR_LDRBS (1<<6) +#define TC_SR_ETRGS (1<<7) +#define TC_SR_CLKSTA (1<<16) +#define TC_SR_MTIOA (1<<17) +#define TC_SR_MTIOB (1<<18) + +//------------- +// Timer/Counter 0 + +#define TC0_BASE (TC_BASE+0x40*0) + +#define TC0_CCR REG(TC0_BASE+0x00) +#define TC0_CMR REG(TC0_BASE+0x04) +#define TC0_CV REG(TC0_BASE+0x10) +#define TC0_RA REG(TC0_BASE+0x14) +#define TC0_RB REG(TC0_BASE+0x18) +#define TC0_RC REG(TC0_BASE+0x1C) +#define TC0_SR REG(TC0_BASE+0x20) +#define TC0_IER REG(TC0_BASE+0x24) +#define TC0_IDR REG(TC0_BASE+0x28) +#define TC0_IMR REG(TC0_BASE+0x2C) + +//------------- +// Timer/Counter 1 + +#define TC1_BASE (TC_BASE+0x40*1) + +#define TC1_CCR REG(TC1_BASE+0x00) +#define TC1_CMR REG(TC1_BASE+0x04) +#define TC1_CV REG(TC1_BASE+0x10) +#define TC1_RA REG(TC1_BASE+0x14) +#define TC1_RB REG(TC1_BASE+0x18) +#define TC1_RC REG(TC1_BASE+0x1C) +#define TC1_SR REG(TC1_BASE+0x20) +#define TC1_IER REG(TC1_BASE+0x24) +#define TC1_IDR REG(TC1_BASE+0x28) +#define TC1_IMR REG(TC1_BASE+0x2C) + +//------------- +// Timer/Counter 2 + +#define TC2_BASE (TC_BASE+0x40*2) + +#define TC2_CCR REG(TC2_BASE+0x00) +#define TC2_CMR REG(TC2_BASE+0x04) +#define TC2_CV REG(TC2_BASE+0x10) +#define TC2_RA REG(TC2_BASE+0x14) +#define TC2_RB REG(TC2_BASE+0x18) +#define TC2_RC REG(TC2_BASE+0x1C) +#define TC2_SR REG(TC2_BASE+0x20) +#define TC2_IER REG(TC2_BASE+0x24) +#define TC2_IDR REG(TC2_BASE+0x28) +#define TC2_IMR REG(TC2_BASE+0x2C) + + #endif -- 2.39.2