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Commit | Line | Data |
---|---|---|
377c0242 | 1 | -- J.STELZNER\r |
2 | -- INFORMATIK-3 LABOR\r | |
3 | -- 23.08.2006\r | |
4 | -- File: VERG_2.VHD\r | |
5 | \r | |
6 | library ieee ;\r | |
7 | use ieee.std_logic_1164.all ;\r | |
8 | \r | |
9 | entity VERG_2 is\r | |
10 | port\r | |
11 | (\r | |
12 | IN_A :in std_logic_vector(1 downto 0);\r | |
13 | IN_B :in std_logic_vector(1 downto 0);\r | |
14 | GLEICH :out std_logic\r | |
15 | );\r | |
16 | end entity VERG_2 ;\r | |
17 | \r | |
18 | architecture VERG_2_DESIGN of VERG_2 is\r | |
19 | \r | |
20 | begin\r | |
21 | \r | |
22 | process (IN_A,IN_B) \r | |
23 | begin \r | |
24 | \r | |
25 | if IN_A = IN_B then GLEICH <= '1';\r | |
26 | else GLEICH <= '0'; \r | |
27 | end if;\r | |
28 | \r | |
29 | end process;\r | |
30 | \r | |
31 | end architecture VERG_2_DESIGN ;\r |