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40a1f26c | 1 | ////////////////////////////////////////////////////////////////////// |
2 | //// //// | |
3 | //// eth_crc.v //// | |
4 | //// //// | |
5 | //// This file is part of the Ethernet IP core project //// | |
6 | //// http://www.opencores.org/projects/ethmac/ //// | |
7 | //// //// | |
8 | //// Author(s): //// | |
9 | //// - Igor Mohor (igorM@opencores.org) //// | |
10 | //// - Novan Hartadi (novan@vlsi.itb.ac.id) //// | |
11 | //// - Mahmud Galela (mgalela@vlsi.itb.ac.id) //// | |
12 | //// //// | |
13 | //// All additional information is avaliable in the Readme.txt //// | |
14 | //// file. //// | |
15 | //// //// | |
16 | ////////////////////////////////////////////////////////////////////// | |
17 | //// //// | |
18 | //// Copyright (C) 2001 Authors //// | |
19 | //// //// | |
20 | //// This source file may be used and distributed without //// | |
21 | //// restriction provided that this copyright statement is not //// | |
22 | //// removed from the file and that any derivative work contains //// | |
23 | //// the original copyright notice and the associated disclaimer. //// | |
24 | //// //// | |
25 | //// This source file is free software; you can redistribute it //// | |
26 | //// and/or modify it under the terms of the GNU Lesser General //// | |
27 | //// Public License as published by the Free Software Foundation; //// | |
28 | //// either version 2.1 of the License, or (at your option) any //// | |
29 | //// later version. //// | |
30 | //// //// | |
31 | //// This source is distributed in the hope that it will be //// | |
32 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// | |
33 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// | |
34 | //// PURPOSE. See the GNU Lesser General Public License for more //// | |
35 | //// details. //// | |
36 | //// //// | |
37 | //// You should have received a copy of the GNU Lesser General //// | |
38 | //// Public License along with this source; if not, download it //// | |
39 | //// from http://www.opencores.org/lgpl.shtml //// | |
40 | //// //// | |
41 | ////////////////////////////////////////////////////////////////////// | |
42 | // | |
43 | // CVS Revision History | |
44 | // | |
45 | // $Log: eth_crc.v,v $ | |
46 | // Revision 1.1 2007-03-20 17:50:56 sithglan | |
47 | // add shit | |
48 | // | |
49 | // Revision 1.3 2002/01/23 10:28:16 mohor | |
50 | // Link in the header changed. | |
51 | // | |
52 | // Revision 1.2 2001/10/19 08:43:51 mohor | |
53 | // eth_timescale.v changed to timescale.v This is done because of the | |
54 | // simulation of the few cores in a one joined project. | |
55 | // | |
56 | // Revision 1.1 2001/08/06 14:44:29 mohor | |
57 | // A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). | |
58 | // Include files fixed to contain no path. | |
59 | // File names and module names changed ta have a eth_ prologue in the name. | |
60 | // File eth_timescale.v is used to define timescale | |
61 | // All pin names on the top module are changed to contain _I, _O or _OE at the end. | |
62 | // Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O | |
63 | // and Mdo_OE. The bidirectional signal must be created on the top level. This | |
64 | // is done due to the ASIC tools. | |
65 | // | |
66 | // Revision 1.1 2001/07/30 21:23:42 mohor | |
67 | // Directory structure changed. Files checked and joind together. | |
68 | // | |
69 | // Revision 1.3 2001/06/19 18:16:40 mohor | |
70 | // TxClk changed to MTxClk (as discribed in the documentation). | |
71 | // Crc changed so only one file can be used instead of two. | |
72 | // | |
73 | // Revision 1.2 2001/06/19 10:38:07 mohor | |
74 | // Minor changes in header. | |
75 | // | |
76 | // Revision 1.1 2001/06/19 10:27:57 mohor | |
77 | // TxEthMAC initial release. | |
78 | // | |
79 | // | |
80 | // | |
81 | ||
82 | ||
83 | `include "timescale.v" | |
84 | ||
85 | module eth_crc (Clk, Reset, Data, Enable, Initialize, Crc, CrcError); | |
86 | ||
87 | ||
88 | parameter Tp = 1; | |
89 | ||
90 | input Clk; | |
91 | input Reset; | |
92 | input [3:0] Data; | |
93 | input Enable; | |
94 | input Initialize; | |
95 | ||
96 | output [31:0] Crc; | |
97 | output CrcError; | |
98 | ||
99 | reg [31:0] Crc; | |
100 | ||
101 | wire [31:0] CrcNext; | |
102 | ||
103 | ||
104 | assign CrcNext[0] = Enable & (Data[0] ^ Crc[28]); | |
105 | assign CrcNext[1] = Enable & (Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29]); | |
106 | assign CrcNext[2] = Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30]); | |
107 | assign CrcNext[3] = Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31]); | |
108 | assign CrcNext[4] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[0]; | |
109 | assign CrcNext[5] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[1]; | |
110 | assign CrcNext[6] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[ 2]; | |
111 | assign CrcNext[7] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[3]; | |
112 | assign CrcNext[8] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[4]; | |
113 | assign CrcNext[9] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[5]; | |
114 | assign CrcNext[10] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[6]; | |
115 | assign CrcNext[11] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[7]; | |
116 | assign CrcNext[12] = (Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30])) ^ Crc[8]; | |
117 | assign CrcNext[13] = (Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31])) ^ Crc[9]; | |
118 | assign CrcNext[14] = (Enable & (Data[3] ^ Data[2] ^ Crc[30] ^ Crc[31])) ^ Crc[10]; | |
119 | assign CrcNext[15] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[11]; | |
120 | assign CrcNext[16] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[12]; | |
121 | assign CrcNext[17] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[13]; | |
122 | assign CrcNext[18] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[14]; | |
123 | assign CrcNext[19] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[15]; | |
124 | assign CrcNext[20] = Crc[16]; | |
125 | assign CrcNext[21] = Crc[17]; | |
126 | assign CrcNext[22] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[18]; | |
127 | assign CrcNext[23] = (Enable & (Data[1] ^ Data[0] ^ Crc[29] ^ Crc[28])) ^ Crc[19]; | |
128 | assign CrcNext[24] = (Enable & (Data[2] ^ Data[1] ^ Crc[30] ^ Crc[29])) ^ Crc[20]; | |
129 | assign CrcNext[25] = (Enable & (Data[3] ^ Data[2] ^ Crc[31] ^ Crc[30])) ^ Crc[21]; | |
130 | assign CrcNext[26] = (Enable & (Data[3] ^ Data[0] ^ Crc[31] ^ Crc[28])) ^ Crc[22]; | |
131 | assign CrcNext[27] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[23]; | |
132 | assign CrcNext[28] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[24]; | |
133 | assign CrcNext[29] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[25]; | |
134 | assign CrcNext[30] = Crc[26]; | |
135 | assign CrcNext[31] = Crc[27]; | |
136 | ||
137 | ||
138 | always @ (posedge Clk or posedge Reset) | |
139 | begin | |
140 | if (Reset) | |
141 | Crc <= #1 32'hffffffff; | |
142 | else | |
143 | if(Initialize) | |
144 | Crc <= #Tp 32'hffffffff; | |
145 | else | |
146 | Crc <= #Tp CrcNext; | |
147 | end | |
148 | ||
149 | assign CrcError = Crc[31:0] != 32'hc704dd7b; // CRC not equal to magic number | |
150 | ||
151 | endmodule |