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40a1f26c | 1 | ////////////////////////////////////////////////////////////////////// |
2 | //// //// | |
3 | //// eth_txstatem.v //// | |
4 | //// //// | |
5 | //// This file is part of the Ethernet IP core project //// | |
6 | //// http://www.opencores.org/projects/ethmac/ //// | |
7 | //// //// | |
8 | //// Author(s): //// | |
9 | //// - Igor Mohor (igorM@opencores.org) //// | |
10 | //// - Novan Hartadi (novan@vlsi.itb.ac.id) //// | |
11 | //// - Mahmud Galela (mgalela@vlsi.itb.ac.id) //// | |
12 | //// //// | |
13 | //// All additional information is avaliable in the Readme.txt //// | |
14 | //// file. //// | |
15 | //// //// | |
16 | ////////////////////////////////////////////////////////////////////// | |
17 | //// //// | |
18 | //// Copyright (C) 2001 Authors //// | |
19 | //// //// | |
20 | //// This source file may be used and distributed without //// | |
21 | //// restriction provided that this copyright statement is not //// | |
22 | //// removed from the file and that any derivative work contains //// | |
23 | //// the original copyright notice and the associated disclaimer. //// | |
24 | //// //// | |
25 | //// This source file is free software; you can redistribute it //// | |
26 | //// and/or modify it under the terms of the GNU Lesser General //// | |
27 | //// Public License as published by the Free Software Foundation; //// | |
28 | //// either version 2.1 of the License, or (at your option) any //// | |
29 | //// later version. //// | |
30 | //// //// | |
31 | //// This source is distributed in the hope that it will be //// | |
32 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// | |
33 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// | |
34 | //// PURPOSE. See the GNU Lesser General Public License for more //// | |
35 | //// details. //// | |
36 | //// //// | |
37 | //// You should have received a copy of the GNU Lesser General //// | |
38 | //// Public License along with this source; if not, download it //// | |
39 | //// from http://www.opencores.org/lgpl.shtml //// | |
40 | //// //// | |
41 | ////////////////////////////////////////////////////////////////////// | |
42 | // | |
43 | // CVS Revision History | |
44 | // | |
45 | // $Log: eth_txstatem.v,v $ | |
46 | // Revision 1.1 2007-03-20 17:50:56 sithglan | |
47 | // add shit | |
48 | // | |
49 | // Revision 1.6 2003/01/30 13:29:08 tadejm | |
50 | // Defer indication changed. | |
51 | // | |
52 | // Revision 1.5 2002/10/30 12:54:50 mohor | |
53 | // State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. | |
54 | // | |
55 | // Revision 1.4 2002/01/23 10:28:16 mohor | |
56 | // Link in the header changed. | |
57 | // | |
58 | // Revision 1.3 2001/10/19 08:43:51 mohor | |
59 | // eth_timescale.v changed to timescale.v This is done because of the | |
60 | // simulation of the few cores in a one joined project. | |
61 | // | |
62 | // Revision 1.2 2001/09/11 14:17:00 mohor | |
63 | // Few little NCSIM warnings fixed. | |
64 | // | |
65 | // Revision 1.1 2001/08/06 14:44:29 mohor | |
66 | // A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). | |
67 | // Include files fixed to contain no path. | |
68 | // File names and module names changed ta have a eth_ prologue in the name. | |
69 | // File eth_timescale.v is used to define timescale | |
70 | // All pin names on the top module are changed to contain _I, _O or _OE at the end. | |
71 | // Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O | |
72 | // and Mdo_OE. The bidirectional signal must be created on the top level. This | |
73 | // is done due to the ASIC tools. | |
74 | // | |
75 | // Revision 1.1 2001/07/30 21:23:42 mohor | |
76 | // Directory structure changed. Files checked and joind together. | |
77 | // | |
78 | // Revision 1.3 2001/06/19 18:16:40 mohor | |
79 | // TxClk changed to MTxClk (as discribed in the documentation). | |
80 | // Crc changed so only one file can be used instead of two. | |
81 | // | |
82 | // Revision 1.2 2001/06/19 10:38:07 mohor | |
83 | // Minor changes in header. | |
84 | // | |
85 | // Revision 1.1 2001/06/19 10:27:57 mohor | |
86 | // TxEthMAC initial release. | |
87 | // | |
88 | // | |
89 | // | |
90 | // | |
91 | ||
92 | ||
93 | `include "timescale.v" | |
94 | ||
95 | ||
96 | module eth_txstatem (MTxClk, Reset, ExcessiveDefer, CarrierSense, NibCnt, IPGT, IPGR1, | |
97 | IPGR2, FullD, TxStartFrm, TxEndFrm, TxUnderRun, Collision, UnderRun, | |
98 | StartTxDone, TooBig, NibCntEq7, NibCntEq15, MaxFrame, Pad, CrcEn, | |
99 | NibbleMinFl, RandomEq0, ColWindow, RetryMax, NoBckof, RandomEqByteCnt, | |
100 | StateIdle, StateIPG, StatePreamble, StateData, StatePAD, StateFCS, | |
101 | StateJam, StateJam_q, StateBackOff, StateDefer, StartFCS, StartJam, | |
102 | StartBackoff, StartDefer, DeferIndication, StartPreamble, StartData, StartIPG | |
103 | ); | |
104 | ||
105 | parameter Tp = 1; | |
106 | ||
107 | input MTxClk; | |
108 | input Reset; | |
109 | input ExcessiveDefer; | |
110 | input CarrierSense; | |
111 | input [6:0] NibCnt; | |
112 | input [6:0] IPGT; | |
113 | input [6:0] IPGR1; | |
114 | input [6:0] IPGR2; | |
115 | input FullD; | |
116 | input TxStartFrm; | |
117 | input TxEndFrm; | |
118 | input TxUnderRun; | |
119 | input Collision; | |
120 | input UnderRun; | |
121 | input StartTxDone; | |
122 | input TooBig; | |
123 | input NibCntEq7; | |
124 | input NibCntEq15; | |
125 | input MaxFrame; | |
126 | input Pad; | |
127 | input CrcEn; | |
128 | input NibbleMinFl; | |
129 | input RandomEq0; | |
130 | input ColWindow; | |
131 | input RetryMax; | |
132 | input NoBckof; | |
133 | input RandomEqByteCnt; | |
134 | ||
135 | ||
136 | output StateIdle; // Idle state | |
137 | output StateIPG; // IPG state | |
138 | output StatePreamble; // Preamble state | |
139 | output [1:0] StateData; // Data state | |
140 | output StatePAD; // PAD state | |
141 | output StateFCS; // FCS state | |
142 | output StateJam; // Jam state | |
143 | output StateJam_q; // Delayed Jam state | |
144 | output StateBackOff; // Backoff state | |
145 | output StateDefer; // Defer state | |
146 | ||
147 | output StartFCS; // FCS state will be activated in next clock | |
148 | output StartJam; // Jam state will be activated in next clock | |
149 | output StartBackoff; // Backoff state will be activated in next clock | |
150 | output StartDefer; // Defer state will be activated in next clock | |
151 | output DeferIndication; | |
152 | output StartPreamble; // Preamble state will be activated in next clock | |
153 | output [1:0] StartData; // Data state will be activated in next clock | |
154 | output StartIPG; // IPG state will be activated in next clock | |
155 | ||
156 | wire StartIdle; // Idle state will be activated in next clock | |
157 | wire StartPAD; // PAD state will be activated in next clock | |
158 | ||
159 | ||
160 | reg StateIdle; | |
161 | reg StateIPG; | |
162 | reg StatePreamble; | |
163 | reg [1:0] StateData; | |
164 | reg StatePAD; | |
165 | reg StateFCS; | |
166 | reg StateJam; | |
167 | reg StateJam_q; | |
168 | reg StateBackOff; | |
169 | reg StateDefer; | |
170 | reg Rule1; | |
171 | ||
172 | ||
173 | // Defining the next state | |
174 | assign StartIPG = StateDefer & ~ExcessiveDefer & ~CarrierSense; | |
175 | ||
176 | assign StartIdle = StateIPG & (Rule1 & NibCnt[6:0] >= IPGT | ~Rule1 & NibCnt[6:0] >= IPGR2); | |
177 | ||
178 | assign StartPreamble = StateIdle & TxStartFrm & ~CarrierSense; | |
179 | ||
180 | assign StartData[0] = ~Collision & (StatePreamble & NibCntEq15 | StateData[1] & ~TxEndFrm); | |
181 | ||
182 | assign StartData[1] = ~Collision & StateData[0] & ~TxUnderRun & ~MaxFrame; | |
183 | ||
184 | assign StartPAD = ~Collision & StateData[1] & TxEndFrm & Pad & ~NibbleMinFl; | |
185 | ||
186 | assign StartFCS = ~Collision & StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & CrcEn | |
187 | | ~Collision & StatePAD & NibbleMinFl & CrcEn; | |
188 | ||
189 | assign StartJam = (Collision | UnderRun) & ((StatePreamble & NibCntEq15) | (|StateData[1:0]) | StatePAD | StateFCS); | |
190 | ||
191 | assign StartBackoff = StateJam & ~RandomEq0 & ColWindow & ~RetryMax & NibCntEq7 & ~NoBckof; | |
192 | ||
193 | assign StartDefer = StateIPG & ~Rule1 & CarrierSense & NibCnt[6:0] <= IPGR1 & NibCnt[6:0] != IPGR2 | |
194 | | StateIdle & CarrierSense | |
195 | | StateJam & NibCntEq7 & (NoBckof | RandomEq0 | ~ColWindow | RetryMax) | |
196 | | StateBackOff & (TxUnderRun | RandomEqByteCnt) | |
197 | | StartTxDone | TooBig; | |
198 | ||
199 | assign DeferIndication = StateIdle & CarrierSense; | |
200 | ||
201 | // Tx State Machine | |
202 | always @ (posedge MTxClk or posedge Reset) | |
203 | begin | |
204 | if(Reset) | |
205 | begin | |
206 | StateIPG <= #Tp 1'b0; | |
207 | StateIdle <= #Tp 1'b0; | |
208 | StatePreamble <= #Tp 1'b0; | |
209 | StateData[1:0] <= #Tp 2'b0; | |
210 | StatePAD <= #Tp 1'b0; | |
211 | StateFCS <= #Tp 1'b0; | |
212 | StateJam <= #Tp 1'b0; | |
213 | StateJam_q <= #Tp 1'b0; | |
214 | StateBackOff <= #Tp 1'b0; | |
215 | StateDefer <= #Tp 1'b1; | |
216 | end | |
217 | else | |
218 | begin | |
219 | StateData[1:0] <= #Tp StartData[1:0]; | |
220 | StateJam_q <= #Tp StateJam; | |
221 | ||
222 | if(StartDefer | StartIdle) | |
223 | StateIPG <= #Tp 1'b0; | |
224 | else | |
225 | if(StartIPG) | |
226 | StateIPG <= #Tp 1'b1; | |
227 | ||
228 | if(StartDefer | StartPreamble) | |
229 | StateIdle <= #Tp 1'b0; | |
230 | else | |
231 | if(StartIdle) | |
232 | StateIdle <= #Tp 1'b1; | |
233 | ||
234 | if(StartData[0] | StartJam) | |
235 | StatePreamble <= #Tp 1'b0; | |
236 | else | |
237 | if(StartPreamble) | |
238 | StatePreamble <= #Tp 1'b1; | |
239 | ||
240 | if(StartFCS | StartJam) | |
241 | StatePAD <= #Tp 1'b0; | |
242 | else | |
243 | if(StartPAD) | |
244 | StatePAD <= #Tp 1'b1; | |
245 | ||
246 | if(StartJam | StartDefer) | |
247 | StateFCS <= #Tp 1'b0; | |
248 | else | |
249 | if(StartFCS) | |
250 | StateFCS <= #Tp 1'b1; | |
251 | ||
252 | if(StartBackoff | StartDefer) | |
253 | StateJam <= #Tp 1'b0; | |
254 | else | |
255 | if(StartJam) | |
256 | StateJam <= #Tp 1'b1; | |
257 | ||
258 | if(StartDefer) | |
259 | StateBackOff <= #Tp 1'b0; | |
260 | else | |
261 | if(StartBackoff) | |
262 | StateBackOff <= #Tp 1'b1; | |
263 | ||
264 | if(StartIPG) | |
265 | StateDefer <= #Tp 1'b0; | |
266 | else | |
267 | if(StartDefer) | |
268 | StateDefer <= #Tp 1'b1; | |
269 | end | |
270 | end | |
271 | ||
272 | ||
273 | // This sections defines which interpack gap rule to use | |
274 | always @ (posedge MTxClk or posedge Reset) | |
275 | begin | |
276 | if(Reset) | |
277 | Rule1 <= #Tp 1'b0; | |
278 | else | |
279 | begin | |
280 | if(StateIdle | StateBackOff) | |
281 | Rule1 <= #Tp 1'b0; | |
282 | else | |
283 | if(StatePreamble | FullD) | |
284 | Rule1 <= #Tp 1'b1; | |
285 | end | |
286 | end | |
287 | ||
288 | ||
289 | ||
290 | endmodule |