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Commit | Line | Data |
---|---|---|
377c0242 | 1 | -- J.STELZNER\r |
2 | -- INFORMATIK-3 LABOR\r | |
3 | -- 23.08.2006\r | |
4 | -- File: CONFIG_WR_SEL.VHD\r | |
5 | \r | |
6 | library IEEE;\r | |
7 | use IEEE.std_logic_1164.all;\r | |
8 | \r | |
9 | entity IO_WR_SEL is\r | |
10 | port\r | |
11 | (\r | |
12 | IO_WR_COM :in std_logic;\r | |
13 | IRDY_REGn :in std_logic;\r | |
14 | TRDYn :in std_logic;\r | |
15 | ADDR_REG :in std_logic_vector(31 downto 0);\r | |
16 | CBE_REGn :in std_logic_vector( 3 downto 0);\r | |
17 | WRITE_XX1_0 :out std_logic;\r | |
18 | WRITE_XX3_2 :out std_logic;\r | |
19 | WRITE_XX5_4 :out std_logic;\r | |
20 | WRITE_XX7_6 :out std_logic \r | |
21 | );\r | |
22 | end entity IO_WR_SEL;\r | |
23 | \r | |
24 | --PCI Byte Enable \r | |
25 | --C/BE[3..0] gueltige Datenbits \r | |
26 | -------------------------------\r | |
27 | -- 0000 AD 31..0\r | |
28 | -- 1000 AD 23..0\r | |
29 | -- 1100 AD 15..0\r | |
30 | -- 1110 AD 7..0\r | |
31 | -- 0011 AD 31..16\r | |
32 | \r | |
33 | architecture IO_WR_SEL_DESIGN of IO_WR_SEL is\r | |
34 | \r | |
35 | signal WR_ENA :std_logic;\r | |
36 | signal ADDR :std_logic_vector( 5 downto 0); \r | |
37 | \r | |
38 | begin\r | |
39 | \r | |
40 | WR_ENA <= '1' when\r | |
41 | IO_WR_COM = '1' and\r | |
42 | IRDY_REGn = '0' and\r | |
43 | TRDYn = '0' else '0';\r | |
44 | \r | |
45 | \r | |
46 | ADDR <= ADDR_REG(3) & ADDR_REG(2) & CBE_REGn;\r | |
47 | \r | |
48 | \r | |
49 | WRITE_XX1_0 <= '1' when WR_ENA = '1' and ADDR = "001100" else '0'; \r | |
50 | WRITE_XX3_2 <= '1' when WR_ENA = '1' and ADDR = "000011" else '0';\r | |
51 | WRITE_XX5_4 <= '1' when WR_ENA = '1' and ADDR = "011100" else '0'; \r | |
52 | WRITE_XX7_6 <= '1' when WR_ENA = '1' and ADDR = "010011" else '0';\r | |
53 | \r | |
54 | end architecture IO_WR_SEL_DESIGN;\r |