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ebba63a9 | 1 | // Copyright (C) 2005 Peio Azkarate, peio@opencores.org\r |
2 | // Copyright (C) 2006 Jeff Carr, jcarr@opencores.org\r | |
3 | // Copyleft GPL v2\r | |
4 | \r | |
5 | module pcidec_new (clk_i, nrst_i, ad_i, cbe_i, idsel_i, bar0_i, memEN_i,\r | |
6 | pciadrLD_i, adrcfg_o, adrmem_o, adr_o, cmd_o);\r | |
7 | \r | |
8 | // General \r | |
9 | input clk_i;\r | |
10 | input nrst_i;\r | |
11 | // pci \r | |
12 | input [31:0] ad_i;\r | |
13 | input [3:0] cbe_i;\r | |
14 | input idsel_i;\r | |
15 | // control\r | |
16 | input [31:25] bar0_i;\r | |
17 | input memEN_i;\r | |
18 | input pciadrLD_i;\r | |
19 | output adrcfg_o;\r | |
20 | output adrmem_o;\r | |
21 | output [24:1] adr_o;\r | |
22 | output [3:0] cmd_o;\r | |
23 | \r | |
24 | reg [31:0] adr;\r | |
25 | reg [3:0] cmd;\r | |
26 | reg idsel_s;\r | |
27 | wire a1;\r | |
28 | \r | |
29 | //+-------------------------------------------------------------------------+\r | |
30 | //| Load PCI Signals |\r | |
31 | //+-------------------------------------------------------------------------+\r | |
32 | \r | |
33 | always @( negedge nrst_i or posedge clk_i )\r | |
34 | begin\r | |
35 | if( nrst_i == 0 )\r | |
36 | begin\r | |
37 | adr <= 23'b1111_1111_1111_1111_1111_111;\r | |
38 | cmd <= 3'b111;\r | |
39 | idsel_s <= 1'b0;\r | |
40 | end\r | |
41 | else\r | |
42 | if ( pciadrLD_i == 1 )\r | |
43 | begin\r | |
44 | adr <= ad_i;\r | |
45 | cmd <= cbe_i;\r | |
46 | idsel_s <= idsel_i;\r | |
47 | end\r | |
48 | end\r | |
49 | \r | |
50 | assign adrmem_o = (\r | |
51 | ( memEN_i == 1'b1 ) &&\r | |
52 | ( adr [31:25] == bar0_i ) &&\r | |
53 | ( adr [1:0] == 2'b00 ) &&\r | |
54 | ( cmd [3:1] == 3'b011 )\r | |
55 | ) ? 1'b1 : 1'b0;\r | |
56 | \r | |
57 | assign adrcfg_o = (\r | |
58 | ( idsel_s == 1'b1 ) &&\r | |
59 | ( adr [1:0] == 2'b00 ) &&\r | |
60 | ( cmd [3:1] == 3'b101 )\r | |
61 | ) ? 1'b1 : 1'b0;\r | |
62 | \r | |
63 | assign a1 = ~ ( cbe_i [3] && cbe_i [2] );\r | |
64 | assign adr_o = {adr [24:2], a1};\r | |
65 | assign cmd_o = cmd;\r | |
66 | \r | |
67 | endmodule\r |