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ebba63a9 | 1 | //\r |
2 | // PCI Parity Generator.\r | |
3 | //\r | |
4 | // PCI Target generates PAR in the data phase of a read cycle. \r | |
5 | // The 1's sum on AD, CBE and PAR is even.\r | |
6 | //\r | |
7 | // Date Version Author Description\r | |
8 | // 2005-05-13 R00A00 PAU First alfa revision (eng)\r | |
9 | //\r | |
10 | // Copyright (C) 2005 Peio Azkarate, peio@opencores.org\r | |
11 | //\r | |
12 | // This source file is free software; you can redistribute it |\r | |
13 | // and/or modify it under the terms of the GNU Lesser General |\r | |
14 | // Public License as published by the Free Software Foundation; |\r | |
15 | // either version 2.1 of the License, or (at your option) any |\r | |
16 | // later version. |\r | |
17 | \r | |
18 | \r | |
19 | module pcipargen_new (clk_i, pcidatout_i, cbe_i, parOE_i, par_o);\r | |
20 | \r | |
21 | input clk_i;\r | |
22 | input [31:0] pcidatout_i;\r | |
23 | input [3:0] cbe_i;\r | |
24 | input parOE_i;\r | |
25 | output par_o;\r | |
26 | \r | |
27 | \r | |
28 | wire [31:0] d;\r | |
29 | wire pardat;\r | |
30 | wire parcbe;\r | |
31 | wire par;\r | |
32 | wire par_s;\r | |
33 | \r | |
34 | assign d = pcidatout_i;\r | |
35 | \r | |
36 | assign pardat = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7] ^ \r | |
37 | d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^ \r | |
38 | d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] ^ \r | |
39 | d[24] ^ d[25] ^ d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[30] ^ d[31];\r | |
40 | \r | |
41 | assign parcbe = cbe_i[0] ^ cbe_i[1] ^ cbe_i[2] ^ cbe_i[3]; \r | |
42 | \r | |
43 | assign par = pardat ^ parcbe;\r | |
44 | \r | |
45 | // PAR\r | |
46 | assign par_o = ( parOE_i == 1 ) ? par_s : 1'bZ;\r | |
47 | \r | |
48 | endmodule\r | |
49 | /*\r | |
50 | component sync\r | |
51 | port (\r | |
52 | clk : in std_logic;\r | |
53 | d : in std_logic;\r | |
54 | q : out std_logic\r | |
55 | );\r | |
56 | end component;\r | |
57 | \r | |
58 | component sync2\r | |
59 | port (\r | |
60 | clk : in std_logic;\r | |
61 | d : in std_logic;\r | |
62 | q : out std_logic\r | |
63 | );\r | |
64 | end component;\r | |
65 | \r | |
66 | begin\r | |
67 | \r | |
68 | \r | |
69 | \r | |
70 | u1: sync2 port map (\r | |
71 | clk => clk_i,\r | |
72 | d => par,\r | |
73 | q => par_s\r | |
74 | );\r | |
75 | \r | |
76 | \r | |
77 | \r | |
78 | \r | |
79 | end rtl;\r | |
80 | */\r |