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40a1f26c | 1 | ////////////////////////////////////////////////////////////////////// |
2 | //// //// | |
3 | //// eth_rxaddrcheck.v //// | |
4 | //// //// | |
5 | //// This file is part of the Ethernet IP core project //// | |
6 | //// http://www.opencores.org/cores/ethmac/ //// | |
7 | //// //// | |
8 | //// Author(s): //// | |
9 | //// - Bill Dittenhofer (billditt@aol.com) //// | |
10 | //// //// | |
11 | //// All additional information is avaliable in the Readme.txt //// | |
12 | //// file. //// | |
13 | //// //// | |
14 | ////////////////////////////////////////////////////////////////////// | |
15 | //// //// | |
16 | //// Copyright (C) 2001 Authors //// | |
17 | //// //// | |
18 | //// This source file may be used and distributed without //// | |
19 | //// restriction provided that this copyright statement is not //// | |
20 | //// removed from the file and that any derivative work contains //// | |
21 | //// the original copyright notice and the associated disclaimer. //// | |
22 | //// //// | |
23 | //// This source file is free software; you can redistribute it //// | |
24 | //// and/or modify it under the terms of the GNU Lesser General //// | |
25 | //// Public License as published by the Free Software Foundation; //// | |
26 | //// either version 2.1 of the License, or (at your option) any //// | |
27 | //// later version. //// | |
28 | //// //// | |
29 | //// This source is distributed in the hope that it will be //// | |
30 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// | |
31 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// | |
32 | //// PURPOSE. See the GNU Lesser General Public License for more //// | |
33 | //// details. //// | |
34 | //// //// | |
35 | //// You should have received a copy of the GNU Lesser General //// | |
36 | //// Public License along with this source; if not, download it //// | |
37 | //// from http://www.opencores.org/lgpl.shtml //// | |
38 | //// //// | |
39 | ////////////////////////////////////////////////////////////////////// | |
40 | // | |
41 | // CVS Revision History | |
42 | // | |
43 | // $Log: eth_rxaddrcheck.v,v $ | |
44 | // Revision 1.1 2007-03-20 17:50:56 sithglan | |
45 | // add shit | |
46 | // | |
47 | // Revision 1.9 2002/11/22 01:57:06 mohor | |
48 | // Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort | |
49 | // synchronized. | |
50 | // | |
51 | // Revision 1.8 2002/11/19 17:34:52 mohor | |
52 | // AddressMiss status is connecting to the Rx BD. AddressMiss is identifying | |
53 | // that a frame was received because of the promiscous mode. | |
54 | // | |
55 | // Revision 1.7 2002/09/04 18:41:06 mohor | |
56 | // Bug when last byte of destination address was not checked fixed. | |
57 | // | |
58 | // Revision 1.6 2002/03/20 15:14:11 mohor | |
59 | // When in promiscous mode some frames were not received correctly. Fixed. | |
60 | // | |
61 | // Revision 1.5 2002/03/02 21:06:32 mohor | |
62 | // Log info was missing. | |
63 | // | |
64 | // | |
65 | // Revision 1.1 2002/02/08 12:51:54 ditt | |
66 | // Initial release of the ethernet addresscheck module. | |
67 | // | |
68 | // | |
69 | // | |
70 | // | |
71 | // | |
72 | ||
73 | ||
74 | `include "timescale.v" | |
75 | ||
76 | ||
77 | module eth_rxaddrcheck(MRxClk, Reset, RxData, Broadcast ,r_Bro ,r_Pro, | |
78 | ByteCntEq2, ByteCntEq3, ByteCntEq4, ByteCntEq5, | |
79 | ByteCntEq6, ByteCntEq7, HASH0, HASH1, | |
80 | CrcHash, CrcHashGood, StateData, RxEndFrm, | |
81 | Multicast, MAC, RxAbort, AddressMiss, PassAll, | |
82 | ControlFrmAddressOK | |
83 | ); | |
84 | ||
85 | parameter Tp = 1; | |
86 | ||
87 | input MRxClk; | |
88 | input Reset; | |
89 | input [7:0] RxData; | |
90 | input Broadcast; | |
91 | input r_Bro; | |
92 | input r_Pro; | |
93 | input ByteCntEq2; | |
94 | input ByteCntEq3; | |
95 | input ByteCntEq4; | |
96 | input ByteCntEq5; | |
97 | input ByteCntEq6; | |
98 | input ByteCntEq7; | |
99 | input [31:0] HASH0; | |
100 | input [31:0] HASH1; | |
101 | input [5:0] CrcHash; | |
102 | input CrcHashGood; | |
103 | input Multicast; | |
104 | input [47:0] MAC; | |
105 | input [1:0] StateData; | |
106 | input RxEndFrm; | |
107 | input PassAll; | |
108 | input ControlFrmAddressOK; | |
109 | ||
110 | output RxAbort; | |
111 | output AddressMiss; | |
112 | ||
113 | wire BroadcastOK; | |
114 | wire ByteCntEq2; | |
115 | wire ByteCntEq3; | |
116 | wire ByteCntEq4; | |
117 | wire ByteCntEq5; | |
118 | wire RxAddressInvalid; | |
119 | wire RxCheckEn; | |
120 | wire HashBit; | |
121 | wire [31:0] IntHash; | |
122 | reg [7:0] ByteHash; | |
123 | reg MulticastOK; | |
124 | reg UnicastOK; | |
125 | reg RxAbort; | |
126 | reg AddressMiss; | |
127 | ||
128 | assign RxAddressInvalid = ~(UnicastOK | BroadcastOK | MulticastOK | r_Pro); | |
129 | ||
130 | assign BroadcastOK = Broadcast & ~r_Bro; | |
131 | ||
132 | assign RxCheckEn = | StateData; | |
133 | ||
134 | // Address Error Reported at end of address cycle | |
135 | // RxAbort clears after one cycle | |
136 | ||
137 | always @ (posedge MRxClk or posedge Reset) | |
138 | begin | |
139 | if(Reset) | |
140 | RxAbort <= #Tp 1'b0; | |
141 | else if(RxAddressInvalid & ByteCntEq7 & RxCheckEn) | |
142 | RxAbort <= #Tp 1'b1; | |
143 | else | |
144 | RxAbort <= #Tp 1'b0; | |
145 | end | |
146 | ||
147 | ||
148 | // This ff holds the "Address Miss" information that is written to the RX BD status. | |
149 | always @ (posedge MRxClk or posedge Reset) | |
150 | begin | |
151 | if(Reset) | |
152 | AddressMiss <= #Tp 1'b0; | |
153 | else if(ByteCntEq7 & RxCheckEn) | |
154 | AddressMiss <= #Tp (~(UnicastOK | BroadcastOK | MulticastOK | (PassAll & ControlFrmAddressOK))); | |
155 | end | |
156 | ||
157 | ||
158 | // Hash Address Check, Multicast | |
159 | always @ (posedge MRxClk or posedge Reset) | |
160 | begin | |
161 | if(Reset) | |
162 | MulticastOK <= #Tp 1'b0; | |
163 | else if(RxEndFrm | RxAbort) | |
164 | MulticastOK <= #Tp 1'b0; | |
165 | else if(CrcHashGood & Multicast) | |
166 | MulticastOK <= #Tp HashBit; | |
167 | end | |
168 | ||
169 | ||
170 | // Address Detection (unicast) | |
171 | // start with ByteCntEq2 due to delay of addres from RxData | |
172 | always @ (posedge MRxClk or posedge Reset) | |
173 | begin | |
174 | if(Reset) | |
175 | UnicastOK <= #Tp 1'b0; | |
176 | else | |
177 | if(RxCheckEn & ByteCntEq2) | |
178 | UnicastOK <= #Tp RxData[7:0] == MAC[47:40]; | |
179 | else | |
180 | if(RxCheckEn & ByteCntEq3) | |
181 | UnicastOK <= #Tp ( RxData[7:0] == MAC[39:32]) & UnicastOK; | |
182 | else | |
183 | if(RxCheckEn & ByteCntEq4) | |
184 | UnicastOK <= #Tp ( RxData[7:0] == MAC[31:24]) & UnicastOK; | |
185 | else | |
186 | if(RxCheckEn & ByteCntEq5) | |
187 | UnicastOK <= #Tp ( RxData[7:0] == MAC[23:16]) & UnicastOK; | |
188 | else | |
189 | if(RxCheckEn & ByteCntEq6) | |
190 | UnicastOK <= #Tp ( RxData[7:0] == MAC[15:8]) & UnicastOK; | |
191 | else | |
192 | if(RxCheckEn & ByteCntEq7) | |
193 | UnicastOK <= #Tp ( RxData[7:0] == MAC[7:0]) & UnicastOK; | |
194 | else | |
195 | if(RxEndFrm | RxAbort) | |
196 | UnicastOK <= #Tp 1'b0; | |
197 | end | |
198 | ||
199 | assign IntHash = (CrcHash[5])? HASH1 : HASH0; | |
200 | ||
201 | always@(CrcHash or IntHash) | |
202 | begin | |
203 | case(CrcHash[4:3]) | |
204 | 2'b00: ByteHash = IntHash[7:0]; | |
205 | 2'b01: ByteHash = IntHash[15:8]; | |
206 | 2'b10: ByteHash = IntHash[23:16]; | |
207 | 2'b11: ByteHash = IntHash[31:24]; | |
208 | endcase | |
209 | end | |
210 | ||
211 | assign HashBit = ByteHash[CrcHash[2:0]]; | |
212 | ||
213 | ||
214 | endmodule |