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Commit | Line | Data |
---|---|---|
377c0242 | 1 | -- J.STELZNER\r |
2 | -- INFORMATIK-3 LABOR\r | |
3 | -- 23.08.2006\r | |
4 | -- File: VERG_8.VHD\r | |
5 | \r | |
6 | library ieee;\r | |
7 | use ieee.std_logic_1164.all;\r | |
8 | \r | |
9 | entity VERG_8 is\r | |
10 | port\r | |
11 | (\r | |
12 | GLEICH :in std_logic_vector(7 downto 0);\r | |
13 | GLEICH_OUT :out std_logic\r | |
14 | );\r | |
15 | \r | |
16 | end entity VERG_8 ;\r | |
17 | \r | |
18 | architecture VERG_8_DESIGN of VERG_8 is\r | |
19 | \r | |
20 | \r | |
21 | begin\r | |
22 | \r | |
23 | -- GLEICH(0) nicht noetig. Addr-Bereich = 16 Byte\r | |
24 | \r | |
25 | -- GLEICH_OUT <= '1' when GLEICH(7 downto 0) = "11111111" else '0'; \r | |
26 | GLEICH_OUT <= '1' when GLEICH(7 downto 1) = "1111111" else '0'; \r | |
27 | \r | |
28 | end architecture VERG_8_DESIGN ;\r |