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ebba63a9 | 1 | // Copyright (C) 2005 Peio Azkarate, peio@opencores.org\r |
2 | // Copyright (C) 2006 Jeff Carr, jcarr@opencores.org\r | |
3 | //\r | |
4 | // I think what this does is handle 16 vs 32 bit pci accesses\r | |
5 | \r | |
6 | module pcidmux ( clk_i, nrst_i, d_io, pcidatout_o, pcidOE_i, wbdatLD_i, wbrgdMX_i,\r | |
7 | wbd16MX_i, wb_dat_i, wb_dat_o, rg_dat_i, rg_dat_o);\r | |
8 | \r | |
9 | input clk_i;\r | |
10 | input nrst_i;\r | |
11 | \r | |
12 | // d_io : inout std_logic_vector(31 downto 0);\r | |
13 | inout [31:0] d_io;\r | |
14 | output [31:0] pcidatout_o;\r | |
15 | \r | |
16 | input pcidOE_i;\r | |
17 | input wbdatLD_i;\r | |
18 | input wbrgdMX_i;\r | |
19 | input wbd16MX_i;\r | |
20 | \r | |
21 | input [15:0] wb_dat_i;\r | |
22 | output [15:0] wb_dat_o;\r | |
23 | input [31:0] rg_dat_i;\r | |
24 | output [31:0] rg_dat_o;\r | |
25 | \r | |
26 | wire [31:0] pcidatin;\r | |
27 | wire [31:0] pcidatout;\r | |
28 | \r | |
29 | reg [15:0] wb_dat_is;\r | |
30 | \r | |
31 | // always @(negedge nrst_i or posedge clk_i or posedge wbdatLD_i or posedge wb_dat_i)\r | |
32 | always @(negedge nrst_i or posedge clk_i)\r | |
33 | begin\r | |
34 | if ( nrst_i == 0 )\r | |
35 | wb_dat_is <= 16'b1111_1111_1111_1111;\r | |
36 | else\r | |
37 | if ( wbdatLD_i == 1 )\r | |
38 | wb_dat_is <= wb_dat_i;\r | |
39 | end\r | |
40 | \r | |
41 | assign pcidatin = d_io;\r | |
42 | assign d_io = (pcidOE_i == 1'b1 ) ? pcidatout : 32'bZ;\r | |
43 | \r | |
44 | assign pcidatout [31:24] = (wbrgdMX_i == 1'b1) ? wb_dat_is [7:0] : rg_dat_i [31:24];\r | |
45 | assign pcidatout [23:16] = (wbrgdMX_i == 1'b1) ? wb_dat_is [15:8] : rg_dat_i [23:16];\r | |
46 | assign pcidatout [15:8] = (wbrgdMX_i == 1'b1) ? wb_dat_is [7:0] : rg_dat_i [15:8];\r | |
47 | assign pcidatout [7:0] = (wbrgdMX_i == 1'b1) ? wb_dat_is [15:8] : rg_dat_i [7:0];\r | |
48 | \r | |
49 | assign pcidatout_o = pcidatout;\r | |
50 | assign rg_dat_o = pcidatin;\r | |
51 | \r | |
52 | assign wb_dat_o [15:8] = (wbd16MX_i == 1'b1) ? pcidatin [23:16] : pcidatin [7:0];\r | |
53 | assign wb_dat_o [7:0] = (wbd16MX_i == 1'b1) ? pcidatin [31:24] : pcidatin [15:8];\r | |
54 | \r | |
55 | endmodule \r |