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40a1f26c | 1 | ////////////////////////////////////////////////////////////////////// |
2 | //// //// | |
3 | //// eth_register.v //// | |
4 | //// //// | |
5 | //// This file is part of the Ethernet IP core project //// | |
6 | //// http://www.opencores.org/projects/ethmac/ //// | |
7 | //// //// | |
8 | //// Author(s): //// | |
9 | //// - Igor Mohor (igorM@opencores.org) //// | |
10 | //// //// | |
11 | //// All additional information is avaliable in the Readme.txt //// | |
12 | //// file. //// | |
13 | //// //// | |
14 | ////////////////////////////////////////////////////////////////////// | |
15 | //// //// | |
16 | //// Copyright (C) 2001, 2002 Authors //// | |
17 | //// //// | |
18 | //// This source file may be used and distributed without //// | |
19 | //// restriction provided that this copyright statement is not //// | |
20 | //// removed from the file and that any derivative work contains //// | |
21 | //// the original copyright notice and the associated disclaimer. //// | |
22 | //// //// | |
23 | //// This source file is free software; you can redistribute it //// | |
24 | //// and/or modify it under the terms of the GNU Lesser General //// | |
25 | //// Public License as published by the Free Software Foundation; //// | |
26 | //// either version 2.1 of the License, or (at your option) any //// | |
27 | //// later version. //// | |
28 | //// //// | |
29 | //// This source is distributed in the hope that it will be //// | |
30 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// | |
31 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// | |
32 | //// PURPOSE. See the GNU Lesser General Public License for more //// | |
33 | //// details. //// | |
34 | //// //// | |
35 | //// You should have received a copy of the GNU Lesser General //// | |
36 | //// Public License along with this source; if not, download it //// | |
37 | //// from http://www.opencores.org/lgpl.shtml //// | |
38 | //// //// | |
39 | ////////////////////////////////////////////////////////////////////// | |
40 | // | |
41 | // CVS Revision History | |
42 | // | |
43 | // $Log: eth_register.v,v $ | |
44 | // Revision 1.1 2007-03-20 17:50:56 sithglan | |
45 | // add shit | |
46 | // | |
47 | // Revision 1.6 2002/08/16 22:10:12 mohor | |
48 | // Synchronous reset added. | |
49 | // | |
50 | // Revision 1.5 2002/08/16 12:33:27 mohor | |
51 | // Parameter ResetValue changed to capital letters. | |
52 | // | |
53 | // Revision 1.4 2002/02/26 16:18:08 mohor | |
54 | // Reset values are passed to registers through parameters | |
55 | // | |
56 | // Revision 1.3 2002/01/23 10:28:16 mohor | |
57 | // Link in the header changed. | |
58 | // | |
59 | // Revision 1.2 2001/10/19 08:43:51 mohor | |
60 | // eth_timescale.v changed to timescale.v This is done because of the | |
61 | // simulation of the few cores in a one joined project. | |
62 | // | |
63 | // Revision 1.1 2001/08/06 14:44:29 mohor | |
64 | // A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). | |
65 | // Include files fixed to contain no path. | |
66 | // File names and module names changed ta have a eth_ prologue in the name. | |
67 | // File eth_timescale.v is used to define timescale | |
68 | // All pin names on the top module are changed to contain _I, _O or _OE at the end. | |
69 | // Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O | |
70 | // and Mdo_OE. The bidirectional signal must be created on the top level. This | |
71 | // is done due to the ASIC tools. | |
72 | // | |
73 | // | |
74 | // | |
75 | // | |
76 | // | |
77 | // | |
78 | // | |
79 | ||
80 | `include "timescale.v" | |
81 | ||
82 | ||
83 | module eth_register(DataIn, DataOut, Write, Clk, Reset, SyncReset); | |
84 | ||
85 | parameter WIDTH = 8; // default parameter of the register width | |
86 | parameter RESET_VALUE = 0; | |
87 | ||
88 | input [WIDTH-1:0] DataIn; | |
89 | ||
90 | input Write; | |
91 | input Clk; | |
92 | input Reset; | |
93 | input SyncReset; | |
94 | ||
95 | output [WIDTH-1:0] DataOut; | |
96 | reg [WIDTH-1:0] DataOut; | |
97 | ||
98 | ||
99 | ||
100 | always @ (posedge Clk or posedge Reset) | |
101 | begin | |
102 | if(Reset) | |
103 | DataOut<=#1 RESET_VALUE; | |
104 | else | |
105 | if(SyncReset) | |
106 | DataOut<=#1 RESET_VALUE; | |
107 | else | |
108 | if(Write) // write | |
109 | DataOut<=#1 DataIn; | |
110 | end | |
111 | ||
112 | ||
113 | ||
114 | endmodule // Register |