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1 | ////////////////////////////////////////////////////////////////////// | |
2 | //// //// | |
3 | //// eth_macstatus.v //// | |
4 | //// //// | |
5 | //// This file is part of the Ethernet IP core project //// | |
6 | //// http://www.opencores.org/projects/ethmac/ //// | |
7 | //// //// | |
8 | //// Author(s): //// | |
9 | //// - Igor Mohor (igorM@opencores.org) //// | |
10 | //// //// | |
11 | //// All additional information is available in the Readme.txt //// | |
12 | //// file. //// | |
13 | //// //// | |
14 | ////////////////////////////////////////////////////////////////////// | |
15 | //// //// | |
16 | //// Copyright (C) 2001, 2002 Authors //// | |
17 | //// //// | |
18 | //// This source file may be used and distributed without //// | |
19 | //// restriction provided that this copyright statement is not //// | |
20 | //// removed from the file and that any derivative work contains //// | |
21 | //// the original copyright notice and the associated disclaimer. //// | |
22 | //// //// | |
23 | //// This source file is free software; you can redistribute it //// | |
24 | //// and/or modify it under the terms of the GNU Lesser General //// | |
25 | //// Public License as published by the Free Software Foundation; //// | |
26 | //// either version 2.1 of the License, or (at your option) any //// | |
27 | //// later version. //// | |
28 | //// //// | |
29 | //// This source is distributed in the hope that it will be //// | |
30 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// | |
31 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// | |
32 | //// PURPOSE. See the GNU Lesser General Public License for more //// | |
33 | //// details. //// | |
34 | //// //// | |
35 | //// You should have received a copy of the GNU Lesser General //// | |
36 | //// Public License along with this source; if not, download it //// | |
37 | //// from http://www.opencores.org/lgpl.shtml //// | |
38 | //// //// | |
39 | ////////////////////////////////////////////////////////////////////// | |
40 | // | |
41 | // CVS Revision History | |
42 | // | |
43 | // $Log: eth_macstatus.v,v $ | |
44 | // Revision 1.1 2007-03-20 17:50:56 sithglan | |
45 | // add shit | |
46 | // | |
47 | // Revision 1.17 2005/03/21 20:07:18 igorm | |
48 | // Some small fixes + some troubles fixed. | |
49 | // | |
50 | // Revision 1.16 2005/02/21 10:42:11 igorm | |
51 | // Defer indication fixed. | |
52 | // | |
53 | // Revision 1.15 2003/01/30 13:28:19 tadejm | |
54 | // Defer indication changed. | |
55 | // | |
56 | // Revision 1.14 2002/11/22 01:57:06 mohor | |
57 | // Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort | |
58 | // synchronized. | |
59 | // | |
60 | // Revision 1.13 2002/11/13 22:30:58 tadejm | |
61 | // Late collision is reported only when not in the full duplex. | |
62 | // Sample is taken (for status) as soon as MRxDV is not valid (regardless | |
63 | // of the received byte cnt). | |
64 | // | |
65 | // Revision 1.12 2002/09/12 14:50:16 mohor | |
66 | // CarrierSenseLost bug fixed when operating in full duplex mode. | |
67 | // | |
68 | // Revision 1.11 2002/09/04 18:38:03 mohor | |
69 | // CarrierSenseLost status is not set when working in loopback mode. | |
70 | // | |
71 | // Revision 1.10 2002/07/25 18:17:46 mohor | |
72 | // InvalidSymbol generation changed. | |
73 | // | |
74 | // Revision 1.9 2002/04/22 13:51:44 mohor | |
75 | // Short frame and ReceivedLengthOK were not detected correctly. | |
76 | // | |
77 | // Revision 1.8 2002/02/18 10:40:17 mohor | |
78 | // Small fixes. | |
79 | // | |
80 | // Revision 1.7 2002/02/15 17:07:39 mohor | |
81 | // Status was not written correctly when frames were discarted because of | |
82 | // address mismatch. | |
83 | // | |
84 | // Revision 1.6 2002/02/11 09:18:21 mohor | |
85 | // Tx status is written back to the BD. | |
86 | // | |
87 | // Revision 1.5 2002/02/08 16:21:54 mohor | |
88 | // Rx status is written back to the BD. | |
89 | // | |
90 | // Revision 1.4 2002/01/23 10:28:16 mohor | |
91 | // Link in the header changed. | |
92 | // | |
93 | // Revision 1.3 2001/10/19 08:43:51 mohor | |
94 | // eth_timescale.v changed to timescale.v This is done because of the | |
95 | // simulation of the few cores in a one joined project. | |
96 | // | |
97 | // Revision 1.2 2001/09/11 14:17:00 mohor | |
98 | // Few little NCSIM warnings fixed. | |
99 | // | |
100 | // Revision 1.1 2001/08/06 14:44:29 mohor | |
101 | // A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). | |
102 | // Include files fixed to contain no path. | |
103 | // File names and module names changed ta have a eth_ prologue in the name. | |
104 | // File eth_timescale.v is used to define timescale | |
105 | // All pin names on the top module are changed to contain _I, _O or _OE at the end. | |
106 | // Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O | |
107 | // and Mdo_OE. The bidirectional signal must be created on the top level. This | |
108 | // is done due to the ASIC tools. | |
109 | // | |
110 | // Revision 1.1 2001/07/30 21:23:42 mohor | |
111 | // Directory structure changed. Files checked and joind together. | |
112 | // | |
113 | // | |
114 | // | |
115 | // | |
116 | // | |
117 | ||
118 | `include "timescale.v" | |
119 | ||
120 | ||
121 | module eth_macstatus( | |
122 | MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, ReceivedPacketGood, RxCrcError, | |
123 | MRxErr, MRxDV, RxStateSFD, RxStateData, RxStatePreamble, RxStateIdle, Transmitting, | |
124 | RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame, | |
125 | InvalidSymbol, MRxD, LatchedCrcError, Collision, CollValid, RxLateCollision, | |
126 | r_RecSmall, r_MinFL, r_MaxFL, ShortFrame, DribbleNibble, ReceivedPacketTooBig, r_HugEn, | |
127 | LoadRxStatus, StartTxDone, StartTxAbort, RetryCnt, RetryCntLatched, MTxClk, MaxCollisionOccured, | |
128 | RetryLimit, LateCollision, LateCollLatched, DeferIndication, DeferLatched, RstDeferLatched, TxStartFrm, | |
129 | StatePreamble, StateData, CarrierSense, CarrierSenseLost, TxUsedData, LatchedMRxErr, Loopback, | |
130 | r_FullD | |
131 | ); | |
132 | ||
133 | ||
134 | ||
135 | parameter Tp = 1; | |
136 | ||
137 | ||
138 | input MRxClk; | |
139 | input Reset; | |
140 | input RxCrcError; | |
141 | input MRxErr; | |
142 | input MRxDV; | |
143 | ||
144 | input RxStateSFD; | |
145 | input [1:0] RxStateData; | |
146 | input RxStatePreamble; | |
147 | input RxStateIdle; | |
148 | input Transmitting; | |
149 | input [15:0] RxByteCnt; | |
150 | input RxByteCntEq0; | |
151 | input RxByteCntGreat2; | |
152 | input RxByteCntMaxFrame; | |
153 | input [3:0] MRxD; | |
154 | input Collision; | |
155 | input [5:0] CollValid; | |
156 | input r_RecSmall; | |
157 | input [15:0] r_MinFL; | |
158 | input [15:0] r_MaxFL; | |
159 | input r_HugEn; | |
160 | input StartTxDone; | |
161 | input StartTxAbort; | |
162 | input [3:0] RetryCnt; | |
163 | input MTxClk; | |
164 | input MaxCollisionOccured; | |
165 | input LateCollision; | |
166 | input DeferIndication; | |
167 | input TxStartFrm; | |
168 | input StatePreamble; | |
169 | input [1:0] StateData; | |
170 | input CarrierSense; | |
171 | input TxUsedData; | |
172 | input Loopback; | |
173 | input r_FullD; | |
174 | ||
175 | ||
176 | output ReceivedLengthOK; | |
177 | output ReceiveEnd; | |
178 | output ReceivedPacketGood; | |
179 | output InvalidSymbol; | |
180 | output LatchedCrcError; | |
181 | output RxLateCollision; | |
182 | output ShortFrame; | |
183 | output DribbleNibble; | |
184 | output ReceivedPacketTooBig; | |
185 | output LoadRxStatus; | |
186 | output [3:0] RetryCntLatched; | |
187 | output RetryLimit; | |
188 | output LateCollLatched; | |
189 | output DeferLatched; | |
190 | input RstDeferLatched; | |
191 | output CarrierSenseLost; | |
192 | output LatchedMRxErr; | |
193 | ||
194 | ||
195 | reg ReceiveEnd; | |
196 | ||
197 | reg LatchedCrcError; | |
198 | reg LatchedMRxErr; | |
199 | reg LoadRxStatus; | |
200 | reg InvalidSymbol; | |
201 | reg [3:0] RetryCntLatched; | |
202 | reg RetryLimit; | |
203 | reg LateCollLatched; | |
204 | reg DeferLatched; | |
205 | reg CarrierSenseLost; | |
206 | ||
207 | wire TakeSample; | |
208 | wire SetInvalidSymbol; // Invalid symbol was received during reception in 100Mbps | |
209 | ||
210 | // Crc error | |
211 | always @ (posedge MRxClk or posedge Reset) | |
212 | begin | |
213 | if(Reset) | |
214 | LatchedCrcError <=#Tp 1'b0; | |
215 | else | |
216 | if(RxStateSFD) | |
217 | LatchedCrcError <=#Tp 1'b0; | |
218 | else | |
219 | if(RxStateData[0]) | |
220 | LatchedCrcError <=#Tp RxCrcError & ~RxByteCntEq0; | |
221 | end | |
222 | ||
223 | ||
224 | // LatchedMRxErr | |
225 | always @ (posedge MRxClk or posedge Reset) | |
226 | begin | |
227 | if(Reset) | |
228 | LatchedMRxErr <=#Tp 1'b0; | |
229 | else | |
230 | if(MRxErr & MRxDV & (RxStatePreamble | RxStateSFD | (|RxStateData) | RxStateIdle & ~Transmitting)) | |
231 | LatchedMRxErr <=#Tp 1'b1; | |
232 | else | |
233 | LatchedMRxErr <=#Tp 1'b0; | |
234 | end | |
235 | ||
236 | ||
237 | // ReceivedPacketGood | |
238 | assign ReceivedPacketGood = ~LatchedCrcError; | |
239 | ||
240 | ||
241 | // ReceivedLengthOK | |
242 | assign ReceivedLengthOK = RxByteCnt[15:0] >= r_MinFL[15:0] & RxByteCnt[15:0] <= r_MaxFL[15:0]; | |
243 | ||
244 | ||
245 | ||
246 | ||
247 | ||
248 | // Time to take a sample | |
249 | //assign TakeSample = |RxStateData & ~MRxDV & RxByteCntGreat2 | | |
250 | assign TakeSample = (|RxStateData) & (~MRxDV) | | |
251 | RxStateData[0] & MRxDV & RxByteCntMaxFrame; | |
252 | ||
253 | ||
254 | // LoadRxStatus | |
255 | always @ (posedge MRxClk or posedge Reset) | |
256 | begin | |
257 | if(Reset) | |
258 | LoadRxStatus <=#Tp 1'b0; | |
259 | else | |
260 | LoadRxStatus <=#Tp TakeSample; | |
261 | end | |
262 | ||
263 | ||
264 | ||
265 | // ReceiveEnd | |
266 | always @ (posedge MRxClk or posedge Reset) | |
267 | begin | |
268 | if(Reset) | |
269 | ReceiveEnd <=#Tp 1'b0; | |
270 | else | |
271 | ReceiveEnd <=#Tp LoadRxStatus; | |
272 | end | |
273 | ||
274 | ||
275 | // Invalid Symbol received during 100Mbps mode | |
276 | assign SetInvalidSymbol = MRxDV & MRxErr & MRxD[3:0] == 4'he; | |
277 | ||
278 | ||
279 | // InvalidSymbol | |
280 | always @ (posedge MRxClk or posedge Reset) | |
281 | begin | |
282 | if(Reset) | |
283 | InvalidSymbol <=#Tp 1'b0; | |
284 | else | |
285 | if(LoadRxStatus & ~SetInvalidSymbol) | |
286 | InvalidSymbol <=#Tp 1'b0; | |
287 | else | |
288 | if(SetInvalidSymbol) | |
289 | InvalidSymbol <=#Tp 1'b1; | |
290 | end | |
291 | ||
292 | ||
293 | // Late Collision | |
294 | ||
295 | reg RxLateCollision; | |
296 | reg RxColWindow; | |
297 | // Collision Window | |
298 | always @ (posedge MRxClk or posedge Reset) | |
299 | begin | |
300 | if(Reset) | |
301 | RxLateCollision <=#Tp 1'b0; | |
302 | else | |
303 | if(LoadRxStatus) | |
304 | RxLateCollision <=#Tp 1'b0; | |
305 | else | |
306 | if(Collision & (~r_FullD) & (~RxColWindow | r_RecSmall)) | |
307 | RxLateCollision <=#Tp 1'b1; | |
308 | end | |
309 | ||
310 | // Collision Window | |
311 | always @ (posedge MRxClk or posedge Reset) | |
312 | begin | |
313 | if(Reset) | |
314 | RxColWindow <=#Tp 1'b1; | |
315 | else | |
316 | if(~Collision & RxByteCnt[5:0] == CollValid[5:0] & RxStateData[1]) | |
317 | RxColWindow <=#Tp 1'b0; | |
318 | else | |
319 | if(RxStateIdle) | |
320 | RxColWindow <=#Tp 1'b1; | |
321 | end | |
322 | ||
323 | ||
324 | // ShortFrame | |
325 | reg ShortFrame; | |
326 | always @ (posedge MRxClk or posedge Reset) | |
327 | begin | |
328 | if(Reset) | |
329 | ShortFrame <=#Tp 1'b0; | |
330 | else | |
331 | if(LoadRxStatus) | |
332 | ShortFrame <=#Tp 1'b0; | |
333 | else | |
334 | if(TakeSample) | |
335 | ShortFrame <=#Tp RxByteCnt[15:0] < r_MinFL[15:0]; | |
336 | end | |
337 | ||
338 | ||
339 | // DribbleNibble | |
340 | reg DribbleNibble; | |
341 | always @ (posedge MRxClk or posedge Reset) | |
342 | begin | |
343 | if(Reset) | |
344 | DribbleNibble <=#Tp 1'b0; | |
345 | else | |
346 | if(RxStateSFD) | |
347 | DribbleNibble <=#Tp 1'b0; | |
348 | else | |
349 | if(~MRxDV & RxStateData[1]) | |
350 | DribbleNibble <=#Tp 1'b1; | |
351 | end | |
352 | ||
353 | ||
354 | reg ReceivedPacketTooBig; | |
355 | always @ (posedge MRxClk or posedge Reset) | |
356 | begin | |
357 | if(Reset) | |
358 | ReceivedPacketTooBig <=#Tp 1'b0; | |
359 | else | |
360 | if(LoadRxStatus) | |
361 | ReceivedPacketTooBig <=#Tp 1'b0; | |
362 | else | |
363 | if(TakeSample) | |
364 | ReceivedPacketTooBig <=#Tp ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0]; | |
365 | end | |
366 | ||
367 | ||
368 | ||
369 | // Latched Retry counter for tx status | |
370 | always @ (posedge MTxClk or posedge Reset) | |
371 | begin | |
372 | if(Reset) | |
373 | RetryCntLatched <=#Tp 4'h0; | |
374 | else | |
375 | if(StartTxDone | StartTxAbort) | |
376 | RetryCntLatched <=#Tp RetryCnt; | |
377 | end | |
378 | ||
379 | ||
380 | // Latched Retransmission limit | |
381 | always @ (posedge MTxClk or posedge Reset) | |
382 | begin | |
383 | if(Reset) | |
384 | RetryLimit <=#Tp 1'h0; | |
385 | else | |
386 | if(StartTxDone | StartTxAbort) | |
387 | RetryLimit <=#Tp MaxCollisionOccured; | |
388 | end | |
389 | ||
390 | ||
391 | // Latched Late Collision | |
392 | always @ (posedge MTxClk or posedge Reset) | |
393 | begin | |
394 | if(Reset) | |
395 | LateCollLatched <=#Tp 1'b0; | |
396 | else | |
397 | if(StartTxDone | StartTxAbort) | |
398 | LateCollLatched <=#Tp LateCollision; | |
399 | end | |
400 | ||
401 | ||
402 | ||
403 | // Latched Defer state | |
404 | always @ (posedge MTxClk or posedge Reset) | |
405 | begin | |
406 | if(Reset) | |
407 | DeferLatched <=#Tp 1'b0; | |
408 | else | |
409 | if(DeferIndication) | |
410 | DeferLatched <=#Tp 1'b1; | |
411 | else | |
412 | if(RstDeferLatched) | |
413 | DeferLatched <=#Tp 1'b0; | |
414 | end | |
415 | ||
416 | ||
417 | // CarrierSenseLost | |
418 | always @ (posedge MTxClk or posedge Reset) | |
419 | begin | |
420 | if(Reset) | |
421 | CarrierSenseLost <=#Tp 1'b0; | |
422 | else | |
423 | if((StatePreamble | (|StateData)) & ~CarrierSense & ~Loopback & ~Collision & ~r_FullD) | |
424 | CarrierSenseLost <=#Tp 1'b1; | |
425 | else | |
426 | if(TxStartFrm) | |
427 | CarrierSenseLost <=#Tp 1'b0; | |
428 | end | |
429 | ||
430 | ||
431 | endmodule |