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Commit | Line | Data |
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1 | -- J.STELZNER\r | |
2 | -- INFORMATIK-3 LABOR\r | |
3 | -- 23.08.2006\r | |
4 | -- File: CONFIG_04H.VHD\r | |
5 | \r | |
6 | library IEEE;\r | |
7 | use IEEE.std_logic_1164.all;\r | |
8 | \r | |
9 | entity CONFIG_04H is\r | |
10 | port\r | |
11 | (\r | |
12 | PCI_CLOCK :in std_logic;\r | |
13 | PCI_RSTn :in std_logic;\r | |
14 | SERR :in std_logic;\r | |
15 | PERR :in std_logic;\r | |
16 | AD_REG :in std_logic_vector(31 downto 0);\r | |
17 | CBE_REGn :in std_logic_vector( 3 downto 0);\r | |
18 | CONF_WR_04H :in std_logic;\r | |
19 | CONF_DATA_04H :out std_logic_vector(31 downto 0)\r | |
20 | );\r | |
21 | end entity CONFIG_04H;\r | |
22 | \r | |
23 | architecture CONFIG_04H_DESIGN of CONFIG_04H is\r | |
24 | \r | |
25 | signal CONF_STATUS :std_logic_vector(31 downto 16);\r | |
26 | signal CONF_COMMAND :std_logic_vector(15 downto 0);\r | |
27 | \r | |
28 | \r | |
29 | begin\r | |
30 | \r | |
31 | --*******************************************************************\r | |
32 | --************* PCI Configuration Space Header "STATUS" *************\r | |
33 | --*******************************************************************\r | |
34 | \r | |
35 | CONF_STATUS(20 downto 16) <= "00000" ;-- Reserved\r | |
36 | CONF_STATUS(21 ) <= '0' ;-- MAS/TAR: "R_O" :'0'= 33MHz / '1'= 66MHz\r | |
37 | CONF_STATUS(22 ) <= '0' ;-- MAS/TAR: "R_O" \r | |
38 | CONF_STATUS(23 ) <= '0' ;-- ???/???: "R_O" : fast back-to-back\r | |
39 | CONF_STATUS(24 ) <= '0' ;-- Master :\r | |
40 | --CONF_STATUS(26 downto 25) <= "00" ;-- Mas/Tar: "R_O" : timing fast for "DEVSEL"\r | |
41 | CONF_STATUS(26 downto 25) <= "01" ;-- Mas/Tar: "R_O" : timing medium for "DEVSEL"\r | |
42 | --CONF_STATUS(26 downto 25) <= "10" ;-- Mas/Tar: "R_O" : timing slow for "DEVSEL"\r | |
43 | --CONF_STATUS(26 downto 25) <= "11" ;-- Mas/Tar: "R_O" : reserved\r | |
44 | CONF_STATUS(27 ) <= '0' ;-- Target : "R_W" : Taget-Abort\r | |
45 | CONF_STATUS(28 ) <= '0' ;-- Master : "R_W" : Taget-Abort\r | |
46 | CONF_STATUS(29 ) <= '0' ;-- Master : "R_W" : Master-Abort\r | |
47 | --CONF_STATUS(30 ) <= SERR ;-- Mas/Tar: "R_W" : SERR\r | |
48 | --CONF_STATUS(31 ) <= PERR ;-- Mas/Tar: "R_W" : PERR\r | |
49 | \r | |
50 | process (PCI_CLOCK,PCI_RSTn) \r | |
51 | begin\r | |
52 | if PCI_RSTn = '0' then CONF_STATUS(30) <= '0';\r | |
53 | CONF_STATUS(31) <= '0';\r | |
54 | \r | |
55 | elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r | |
56 | \r | |
57 | if CONF_WR_04H = '1' and CBE_REGn(3) = '0' then \r | |
58 | \r | |
59 | CONF_STATUS(30) <= not (AD_REG(30) and CONF_STATUS(30)); \r | |
60 | CONF_STATUS(31) <= not (AD_REG(31) and CONF_STATUS(31));\r | |
61 | \r | |
62 | else CONF_STATUS(30) <= SERR or CONF_STATUS(30);\r | |
63 | CONF_STATUS(31) <= PERR or CONF_STATUS(31);\r | |
64 | \r | |
65 | end if; \r | |
66 | end if; \r | |
67 | end process;\r | |
68 | \r | |
69 | --*******************************************************************\r | |
70 | --*********** PCI Configuration Space Header "COMMAND" **************\r | |
71 | --*******************************************************************\r | |
72 | \r | |
73 | -- CONF_COMMAND( 0) <= '0';-- I/O Space accesses ???\r | |
74 | -- CONF_COMMAND( 1) <= '0';-- Mem Space accesses ???\r | |
75 | -- CONF_COMMAND( 2) <= '0';-- abillity to act as a master on the PCI bus \r | |
76 | -- CONF_COMMAND( 3) <= '0';-- Special Cycle ???\r | |
77 | -- CONF_COMMAND( 4) <= '0';-- Master ??? \r | |
78 | -- CONF_COMMAND( 5) <= '0';-- VGA ???\r | |
79 | -- CONF_COMMAND( 6) <= '0';-- Party checking enable/disable\r | |
80 | CONF_COMMAND( 7) <= '0';-- address/data stepping ???\r | |
81 | -- CONF_COMMAND( 8) <= '0';-- enable/disable "PCI_SERRn"\r | |
82 | -- CONF_COMMAND( 9) <= '0';-- fast back-to-back\r | |
83 | -- CONF_COMMAND(10) <= '0';-- Reserved\r | |
84 | -- CONF_COMMAND(11) <= '0';-- Reserved\r | |
85 | -- CONF_COMMAND(12) <= '0';-- Reserved\r | |
86 | -- CONF_COMMAND(13) <= '0';-- Reserved\r | |
87 | -- CONF_COMMAND(14) <= '0';-- Reserved\r | |
88 | -- CONF_COMMAND(15) <= '0';-- Reserved\r | |
89 | \r | |
90 | process (PCI_CLOCK,PCI_RSTn) \r | |
91 | begin\r | |
92 | if PCI_RSTn = '0' then CONF_COMMAND(15 downto 8) <= (others =>'0');\r | |
93 | CONF_COMMAND( 6 downto 0) <= (others =>'0');\r | |
94 | \r | |
95 | elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r | |
96 | \r | |
97 | if CONF_WR_04H = '1'and CBE_REGn(1) = '0' then \r | |
98 | \r | |
99 | CONF_COMMAND(15 downto 8) <= AD_REG(15 downto 8);\r | |
100 | else CONF_COMMAND(15 downto 8) <= CONF_COMMAND(15 downto 8);\r | |
101 | end if;\r | |
102 | \r | |
103 | \r | |
104 | if CONF_WR_04H = '1'and CBE_REGn(0) = '0' then \r | |
105 | \r | |
106 | CONF_COMMAND( 6 downto 0) <= AD_REG( 6 downto 0);\r | |
107 | else CONF_COMMAND( 6 downto 0) <= CONF_COMMAND( 6 downto 0);\r | |
108 | end if;\r | |
109 | \r | |
110 | end if;\r | |
111 | end process;\r | |
112 | \r | |
113 | CONF_DATA_04H <= CONF_STATUS & CONF_COMMAND; \r | |
114 | \r | |
115 | end architecture CONFIG_04H_DESIGN;\r |