MD_PAD_IO : INOUT std_logic;
MDC_PAD_O : OUT std_logic;
+ PHY_CLOCK : OUT std_logic;
+
LED_2 : OUT std_logic
);
end ethernet;
);
end component;
+component phydcm is
+port ( CLKIN_IN : in std_logic;
+ RST_IN : in std_logic;
+ CLKFX_OUT : out std_logic;
+ CLKIN_IBUFG_OUT : out std_logic;
+ CLK0_OUT : out std_logic;
+ LOCKED_OUT : out std_logic);
+end component;
+
signal pci_rst_o : std_logic;
signal pci_rst_oe_o : std_logic;
signal pci_inta_o : std_logic;
trig0 => trig0
);
+eth_dcm : phydcm
+port map (
+ CLKIN_IN => PCI_CLOCK,
+ RST_IN => not PCI_RSTn,
+ CLKFX_OUT => PHY_CLOCK
+-- CLKIN_IBUFG_OUT
+-- CLK0_OUT
+-- LOCKED_OUT
+ );
+
end architecture ethernet_arch;