signal wb_err : std_logic;\r
signal wb_int : std_logic;\r
\r
+signal fifo_din : std_logic_vector(7 downto 0);\r
+signal fifo_dout : std_logic_vector(7 downto 0);\r
+signal fifo_we : std_logic;\r
+signal fifo_re : std_logic;\r
+\r
+\r
\r
begin\r
\r
wb_int_i => wb_int\r
-- debug_init => LED3,\r
-- debug_access => LED2\r
- );\r
+);\r
+\r
+my_generic_fifo: component generic_fifo_sc_a\r
+port map(\r
+ clk => PCI_CLK,\r
+ rst => PCI_nRES,\r
+-- clr =>\r
+ din => fifo_din,\r
+ we => fifo_we,\r
+ dout => fifo_dout,\r
+ re => fifo_re\r
+-- full => ,\r
+-- full_r => ,\r
+-- empty => ,\r
+-- empty_r => ,\r
+-- full_n => ,\r
+-- full_n_r => ,\r
+-- empty_n => ,\r
+-- empty_n_r => ,\r
+-- level => ,\r
+);\r
+\r
+my_fifo: component wb_fifo\r
+port map(\r
+ clk_i => PCI_CLK,\r
+ nrst_i => PCI_nRES,\r
+\r
+ wb_adr_i => wb_adr,\r
+ wb_dat_o => wb_dat_out,\r
+ wb_dat_i => wb_dat_in,\r
+ wb_sel_i => wb_sel,\r
+ wb_we_i => wb_we,\r
+ wb_stb_i => wb_stb,\r
+ wb_cyc_i => wb_cyc,\r
+ wb_ack_o => wb_ack,\r
+ wb_err_o => wb_err,\r
+ wb_int_o => wb_int,\r
+\r
+ fifo_data_i => fifo_dout,\r
+ fifo_data_o => fifo_din,\r
+\r
+ fifo_we_out => fifo_we,\r
+ fifo_re_out => fifo_re\r
+);\r
\r
my_heartbeat: component heartbeat\r
port map( \r