SPC_RDY_OUT : Out std_logic;\r
SR_ERROR : Out std_logic;\r
PAR_SER_IN : Out std_logic_vector (7 downto 0);\r
+ SER_PAR_OUT : Out std_logic_vector (7 downto 0);\r
SYNC_FLAG : Out std_logic_vector (7 downto 0) );\r
end component;\r
\r
LED_4 <= '0';\r
LED_5 <= not watch;\r
PCI_INTAn <= watch;\r
- trig0(7 downto 0) <= (0 => watch, others => '0');\r
+ trig0(7 downto 0) <= (0 => watch, 1 => R_FIFO_READn, 2 => R_FIFO_WRITEn, 3 => S_FIFO_READn, 4 => S_FIFO_WRITEn, others => '0');\r
data(0) <= watch;\r
\r
data(1) <= R_EFn;\r
data(16) <= SPC_RDY_IN;\r
data(17) <= SERIAL_OUT;\r
data(18) <= SPC_RDY_OUT;\r
+ data(34 downto 27) <= R_FIFO_Q_OUT;\r
\r
I19 : MESS_1_TB\r
Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r