--- $Id: fifo_io_control.vhd,v 1.2 2007-03-11 09:14:58 sithglan Exp $
+-- $Id: fifo_io_control.vhd,v 1.3 2007-03-11 12:24:35 sithglan Exp $
library IEEE;
use IEEE.std_logic_1164.all;
process (PCI_CLOCK)
begin
- if (rising_edge(PCI_CLOCK)) then
+ if (PCI_CLOCK'event and PCI_CLOCK = '1') then
if (RESET = '1') then
S_FIFO_WRITEn <= '1';
SIG_S_ERROR <= '0';