X-Git-Url: http://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/2268f768ef2c56c06901b433175700a68d371dcc..b98e21a53a485e26aca52a3b8c9e0406c25f3ab0:/ethernet/source/pci/pci_user_constants.v

diff --git a/ethernet/source/pci/pci_user_constants.v b/ethernet/source/pci/pci_user_constants.v
index 2415dce..af419f1 100644
--- a/ethernet/source/pci/pci_user_constants.v
+++ b/ethernet/source/pci/pci_user_constants.v
@@ -39,7 +39,10 @@
 // CVS Revision History
 //
 // $Log: pci_user_constants.v,v $
-// Revision 1.2  2007-03-20 20:56:19  sithglan
+// Revision 1.3  2007-03-21 11:53:06  sithglan
+// enable address translation
+//
+// Revision 1.2  2007/03/20 20:56:19  sithglan
 // changes
 //
 // Revision 1.1  2007/03/20 17:50:56  sithglan
@@ -140,8 +143,8 @@
 
 // these two defines allow user to select active high or low output enables on PCI bus signals, depending on
 // output buffers instantiated. Xilinx FPGAs use active low output enables.
-// `define ACTIVE_LOW_OE
-`define ACTIVE_HIGH_OE
+`define ACTIVE_LOW_OE
+//`define ACTIVE_HIGH_OE
 
 // HOST/GUEST implementation selection - see design document and specification for description of each implementation
 // only one can be defined at same time
@@ -281,7 +284,7 @@
 // addresses will pass through bridge unchanged, regardles of address translation enable bits.
 // Address translation also slows down the decoding
 //When  ADDR_TRAN_IMPL this define is present then adress translation is enabled after reset.
-//`define ADDR_TRAN_IMPL
+`define ADDR_TRAN_IMPL
 
 // decode speed for WISHBONE definition - initial cycle on WISHBONE bus will take 1 WS for FAST, 2 WSs for MEDIUM and 3 WSs for slow.
 // slower decode speed can be used, to provide enough time for address to be decoded.