From: michael Date: Sat, 10 Mar 2007 14:07:35 +0000 (+0000) Subject: chipscope X-Git-Url: http://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/commitdiff_plain/1afff8d481bb2d34c54b1c669b400bf706a9e7b6?hp=bba7a6d51635a1cb7d31bdfc03b1a66ee9df336b chipscope --- diff --git a/dhwk/dhwk.cpj b/dhwk/dhwk.cpj new file mode 100644 index 0000000..6edc2bd --- /dev/null +++ b/dhwk/dhwk.cpj @@ -0,0 +1,659 @@ +#ChipScope Pro Analyzer Project File, Version 3.0 +#Sat Mar 10 15:06:53 GMT+01:00 2007 +deviceChain.deviceName0=XCF02S +deviceChain.deviceName1=XCF04S +deviceChain.deviceName2=XC3S1500 +deviceChain.iRLength0=8 +deviceChain.iRLength1=8 +deviceChain.iRLength2=6 +deviceChain.name0=MyDevice0 +deviceChain.name1=MyDevice1 +deviceChain.name2=MyDevice2 +deviceIds=050450930504609301434093 +mdiAreaHeight=0.7993890020366599 +mdiAreaHeightLast=0.7993890020366599 +mdiCount=2 +mdiDevice0=2 +mdiDevice1=2 +mdiType0=1 +mdiType1=0 +mdiUnit0=0 +mdiUnit1=0 +navigatorHeight=0.17922606924643583 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+unit.2.0.port.0.s.6.orderindex=-1 +unit.2.0.port.0.s.6.visible=1 +unit.2.0.port.0.s.7.alias= +unit.2.0.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.0.s.7.name=TriggerPort0[7] +unit.2.0.port.0.s.7.orderindex=-1 +unit.2.0.port.0.s.7.visible=1 +unit.2.0.portcount=1 +unit.2.0.samplesPerTrigger=1 +unit.2.0.triggerCapture=1 +unit.2.0.triggerNSamplesTS=0 +unit.2.0.triggerPosition=0 +unit.2.0.triggerWindowCount=1 +unit.2.0.triggerWindowDepth=1024 +unit.2.0.triggerWindowTS=0 +unit.2.0.username=MyILA0 +unit.2.0.waveform.count=33 +unit.2.0.waveform.posn.0.channel=2147483646 +unit.2.0.waveform.posn.0.name=PCI +unit.2.0.waveform.posn.0.radix=1 +unit.2.0.waveform.posn.0.type=bus +unit.2.0.waveform.posn.1.channel=32 +unit.2.0.waveform.posn.1.name=PCI_INTAn +unit.2.0.waveform.posn.1.type=signal +unit.2.0.waveform.posn.10.channel=41 +unit.2.0.waveform.posn.10.name=DataPort[41] +unit.2.0.waveform.posn.10.type=signal +unit.2.0.waveform.posn.11.channel=42 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+unit.2.0.waveform.posn.62.name=DataPort[63] +unit.2.0.waveform.posn.62.type=signal +unit.2.0.waveform.posn.63.channel=63 +unit.2.0.waveform.posn.63.name=DataPort[63] +unit.2.0.waveform.posn.63.type=signal +unit.2.0.waveform.posn.64.channel=63 +unit.2.0.waveform.posn.64.name=DataPort[63] +unit.2.0.waveform.posn.64.type=signal +unit.2.0.waveform.posn.7.channel=38 +unit.2.0.waveform.posn.7.name=DataPort[38] +unit.2.0.waveform.posn.7.type=signal +unit.2.0.waveform.posn.8.channel=39 +unit.2.0.waveform.posn.8.name=DataPort[39] +unit.2.0.waveform.posn.8.type=signal +unit.2.0.waveform.posn.9.channel=40 +unit.2.0.waveform.posn.9.name=DataPort[40] +unit.2.0.waveform.posn.9.type=signal diff --git a/dhwk/icon.arg b/dhwk/icon.arg new file mode 100644 index 0000000..fc56ce1 --- /dev/null +++ b/dhwk/icon.arg @@ -0,0 +1,8 @@ +# +# Usage: generate.exe icon -f= +# +-compname=icon +-numports=1 +-devicefamily=Spartan3 +-bscanchain=1 +-outputdirectory=. diff --git a/dhwk/ila.arg b/dhwk/ila.arg new file mode 100644 index 0000000..e206017 --- /dev/null +++ b/dhwk/ila.arg @@ -0,0 +1,16 @@ +# +# Usage: generate.exe ila -f= +# +-compname=ila +-outputdirectory=. +-datadepth=1024 +-datawidth=64 +-numtrigports=1 +-trigportwidth0=8 +-nummatchunits=1 +-mtrigport0=0 +-mtype0=0 +-enablestoragequal +-devicefamily=Spartan3 +-srl16type=2 +-createcdc diff --git a/dhwk/source/top.vhd b/dhwk/source/top.vhd index a79c470..dda8be1 100644 --- a/dhwk/source/top.vhd +++ b/dhwk/source/top.vhd @@ -91,6 +91,9 @@ architecture SCHEMATIC of dhwk is signal SERIAL_OUT : std_logic; signal SPC_RDY_OUT : std_logic; signal watch : std_logic; + signal control0 : std_logic_vector(35 downto 0); + signal data : std_logic_vector(63 downto 0); + signal trig0 : std_logic_vector(7 downto 0); component MESS_1_TB Port ( DEVSELn : In std_logic; @@ -221,6 +224,24 @@ component fifo_generator_v3_2 prog_full: OUT std_logic); end component; +component icon +port + ( + control0 : out std_logic_vector(35 downto 0) + ); +end component; + + component ila + port + ( + control : in std_logic_vector(35 downto 0); + clk : in std_logic; + data : in std_logic_vector(63 downto 0); + trig0 : in std_logic_vector(7 downto 0) + ); + end component; + + begin SERIAL_IN <= SERIAL_OUT; SPC_RDY_IN <= SPC_RDY_OUT; @@ -229,6 +250,28 @@ begin LED_4 <= '0'; LED_5 <= not watch; PCI_INTAn <= watch; + trig0(7 downto 0) <= (others => '0'); + data(31 downto 0) <= PCI_AD(31 downto 0); + data(32) <= watch; + + data(33) <= R_EFn; + data(34) <= R_HFn; + data(35) <= R_FFn; + data(36) <= R_FIFO_READn; + data(37) <= R_FIFO_RESETn; + data(38) <= R_FIFO_RTn; + data(39) <= R_FIFO_WRITEn; + data(40) <= S_EFn; + data(41) <= S_HFn; + data(42) <= S_FFn; + data(43) <= S_FIFO_READn; + data(44) <= S_FIFO_RESETn; + data(45) <= S_FIFO_RTn; + data(46) <= S_FIFO_WRITEn; + data(47) <= SERIAL_IN; + data(48) <= SPC_RDY_IN; + data(49) <= SERIAL_OUT; + data(50) <= SPC_RDY_OUT; I19 : MESS_1_TB Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1, @@ -321,4 +364,19 @@ send_fifo : fifo_generator_v3_2 empty => S_EFn, full => S_FFn, prog_full => S_HFn); + + i_icon : icon + port map + ( + control0 => control0 + ); + + i_ila : ila + port map + ( + control => control0, + clk => PCI_CLOCK, + data => data, + trig0 => trig0 + ); end SCHEMATIC;