From a76e12bdfc68f955f1cedd0c928fba9372a55d07 Mon Sep 17 00:00:00 2001
From: michael <michael>
Date: Sat, 10 Mar 2007 15:48:06 +0000
Subject: [PATCH] other watched signals

---
 dhwk/ila.arg                 |  4 +--
 dhwk/source/fifo_control.vhd |  5 +++-
 dhwk/source/top.vhd          | 47 ++++++++++++++++++------------------
 3 files changed, 30 insertions(+), 26 deletions(-)

diff --git a/dhwk/ila.arg b/dhwk/ila.arg
index e206017..2d1a318 100644
--- a/dhwk/ila.arg
+++ b/dhwk/ila.arg
@@ -3,8 +3,8 @@
 #
 -compname=ila
 -outputdirectory=.
--datadepth=1024
--datawidth=64
+-datadepth=8192
+-datawidth=36
 -numtrigports=1
 -trigportwidth0=8
 -nummatchunits=1
diff --git a/dhwk/source/fifo_control.vhd b/dhwk/source/fifo_control.vhd
index 7c9ce96..1c2d52e 100644
--- a/dhwk/source/fifo_control.vhd
+++ b/dhwk/source/fifo_control.vhd
@@ -43,7 +43,8 @@ entity FIFO_CONTROL is
              SERIAL_OUT : Out   std_logic;
              SPC_RDY_OUT : Out   std_logic;
              SR_ERROR : Out   std_logic;
-             SYNC_FLAG : Out   std_logic_vector (7 downto 0) );
+             SYNC_FLAG : Out   std_logic_vector (7 downto 0);
+	     PAR_SER_IN : Out std_logic_vector (7 downto 0));
 end FIFO_CONTROL;
 
 architecture SCHEMATIC of FIFO_CONTROL is
@@ -127,6 +128,8 @@ architecture SCHEMATIC of FIFO_CONTROL is
 begin
 
    SYNC_FLAG <= SYNC_FLAG_DUMMY;
+   PAR_SER_IN <= S_FIFO_Q_OUT;
+
 
    RESERVE <= gnd;
    I23 : SER_PAR_CON
diff --git a/dhwk/source/top.vhd b/dhwk/source/top.vhd
index dda8be1..e2f307c 100644
--- a/dhwk/source/top.vhd
+++ b/dhwk/source/top.vhd
@@ -92,7 +92,7 @@ architecture SCHEMATIC of dhwk is
    signal SPC_RDY_OUT : std_logic;
    signal watch : std_logic;
    signal control0       : std_logic_vector(35 downto 0);
-   signal data       : std_logic_vector(63 downto 0);
+   signal data       : std_logic_vector(35 downto 0);
    signal trig0      : std_logic_vector(7 downto 0);
 
    component MESS_1_TB
@@ -169,6 +169,7 @@ architecture SCHEMATIC of dhwk is
              SERIAL_OUT : Out   std_logic;
              SPC_RDY_OUT : Out   std_logic;
              SR_ERROR : Out   std_logic;
+	     PAR_SER_IN : Out std_logic_vector (7 downto 0);
              SYNC_FLAG : Out   std_logic_vector (7 downto 0) );
    end component;
 
@@ -236,7 +237,7 @@ end component;
     (
       control     : in    std_logic_vector(35 downto 0);
       clk         : in    std_logic;
-      data        : in    std_logic_vector(63 downto 0);
+      data        : in    std_logic_vector(35 downto 0);
       trig0       : in    std_logic_vector(7 downto 0)
     );
   end component;
@@ -250,28 +251,27 @@ begin
 	LED_4 <= '0';
 	LED_5 <= not watch;
 	PCI_INTAn <= watch;
-	trig0(7 downto 0) <= (others => '0');
-	data(31 downto 0) <= PCI_AD(31 downto 0);
-	data(32) <= watch;
+	trig0(7 downto 0) <= (0 => watch, others => '0');
+	data(0) <= watch;
 	
-	data(33) <= R_EFn;
-	data(34) <= R_HFn;
-	data(35) <= R_FFn;
-	data(36) <= R_FIFO_READn;
-	data(37) <= R_FIFO_RESETn;
-	data(38) <= R_FIFO_RTn;
-	data(39) <= R_FIFO_WRITEn;
-	data(40) <= S_EFn;
-	data(41) <= S_HFn;
-	data(42) <= S_FFn;
-	data(43) <= S_FIFO_READn;
-	data(44) <= S_FIFO_RESETn;
-	data(45) <= S_FIFO_RTn;
-	data(46) <= S_FIFO_WRITEn;
-	data(47) <= SERIAL_IN;
-	data(48) <= SPC_RDY_IN;
-	data(49) <= SERIAL_OUT;
-	data(50) <= SPC_RDY_OUT;
+	data(1) <= R_EFn;
+	data(2) <= R_HFn;
+	data(3) <= R_FFn;
+	data(4) <= R_FIFO_READn;
+	data(5) <= R_FIFO_RESETn;
+	data(6) <= R_FIFO_RTn;
+	data(7) <= R_FIFO_WRITEn;
+	data(8) <= S_EFn;
+	data(9) <= S_HFn;
+	data(10) <= S_FFn;
+	data(11) <= S_FIFO_READn;
+	data(12) <= S_FIFO_RESETn;
+	data(13) <= S_FIFO_RTn;
+	data(14) <= S_FIFO_WRITEn;
+	data(15) <= SERIAL_IN;
+	data(16) <= SPC_RDY_IN;
+	data(17) <= SERIAL_OUT;
+	data(18) <= SPC_RDY_OUT;
 
    I19 : MESS_1_TB
       Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,
@@ -313,6 +313,7 @@ begin
                  S_FIFO_RETRANSMITn=>S_FIFO_RTn,
                  S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,
                  SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,
+		 PAR_SER_IN(7 downto 0)=>data(26 downto 19),
                  SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );
    I1 : PCI_TOP
       Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),
-- 
2.39.5