[fpga-games] / galaxian / src / mc_vga_if.v

//===============================================================================\r
// FPGA VGA INTERFACE  FOR ALTERA CYCLONE & XILINX SPARTAN2E\r
//\r
// Version : 2.00\r
//\r
// Copyright(c) 2003 - 2004 Katsumi Degawa , All rights reserved\r
//\r
// based on a design by Tatsuyuki Satoh\r
//\r
// Important !\r
//\r
// This program is freeware for non-commercial use. \r
// An author does no guarantee about this program.\r
// You can use this under your own risk.\r
//\r
// 2004- 9-18 added SPARTAN2E DEVIDE . K.DEGAWA\r
//================================================================================\r
`include "src/mc_conf.v"\r
\r
module mc_vga_if(\r
\r
I_CLK_1,\r
I_CLK_2,\r
I_R,\r
I_G,\r
I_B,\r
I_H_SYNC,\r
I_V_SYNC,\r
\r
O_R,\r
O_G,\r
O_B,\r
O_H_SYNCn,\r
O_V_SYNCn\r
\r
);\r
\r
// input signals\r
input I_CLK_1;        // 6.144MHz  input pixel clock\r
input I_CLK_2;       // 12.288Mhz output pixel clock\r
input [2:0]I_R;        // R in\r
input [2:0]I_G;        // G in\r
input [1:0]I_B;        // B in\r
input I_H_SYNC;        // HSYNC input (16KHz)\r
input I_V_SYNC;        // VSYNC input (60Hz)\r
\r
// output signals\r
output [2:0]O_R;       // R out\r
output [2:0]O_G;       // G out\r
output [1:0]O_B;       // B out\r
output O_H_SYNCn;      // HSYNC output\r
output O_V_SYNCn;      // VSYNC output\r
\r
//---------------------------------------------------------------------------\r
// setup parameter\r
//---------------------------------------------------------------------------\r
\r
parameter H_COUNT  = 384;        // number of pixels in H-SCAN\r
parameter HS_POS   = 16;         // HSYNC position \r
parameter HS_WIDTH = HS_POS+8;   // HSYNC width / pixel\r
parameter VS_WIDTH = 8;          // VSYNC width / HSYNC_OUT\r
\r
//---------------------------------------------------------------------------\r
// input timming\r
//---------------------------------------------------------------------------\r
reg    [8:0]Hpos_in;     // input capture postion\r
reg    L_Hsync_i;\r
wire   HP_in = ~L_Hsync_i & I_H_SYNC;\r
always@(posedge I_CLK_1)\r
begin\r
   Hpos_in   <= HP_in ? 0: Hpos_in + 1;\r
   L_Hsync_i <= I_H_SYNC;\r
end\r
\r
//---------------------------------------------------------------------------\r
//output timming\r
//---------------------------------------------------------------------------\r
reg    [8:0]Hpos_out;\r
reg    L_Hsync_o;\r
wire   HP_out = ~L_Hsync_o & I_H_SYNC;\r
wire   HP_ret = HP_out | (Hpos_out == H_COUNT-1);\r
\r
always@(posedge I_CLK_2)\r
begin\r
   Hpos_out  <= HP_ret ? 0:Hpos_out + 1;\r
   L_Hsync_o <= I_H_SYNC;\r
end\r
\r
reg    O_Hsync;\r
always@(posedge I_CLK_2)\r
begin\r
   case(Hpos_out)\r
      HS_POS  :O_Hsync <= 1'b1;\r
      HS_WIDTH:O_Hsync <= 1'b0;\r
      default :;\r
   endcase\r
end\r
\r
//---------------------------------------------------------------------------\r
// RGB capture(portA) & output(portB)\r
//---------------------------------------------------------------------------\r
wire   [7:0]rgb_in = {I_R,I_G,I_B};       // RGB input\r
wire   [7:0]rgb_out;                      // RGB output\r
\r
`ifdef DEVICE_CYCLONE\r
alt_ram_512_8_d double_scan_ram(\r
\r
.clock_a(I_CLK_1),\r
.address_a(Hpos_in),\r
.q_a(),\r
.data_a(rgb_in),\r
.wren_a(1'b1),\r
.enable_a(1'b1),\r
.aclr_a(1'b0),\r
\r
.clock_b(I_CLK_2),\r
.address_b(Hpos_out),\r
.q_b(rgb_out),\r
.data_b(4'h0),\r
.wren_b(1'b0),\r
.enable_b(1'b1),\r
.aclr_b(1'b0)\r
\r
);\r
`endif\r
`ifdef DEVICE_SPARTAN2E\r
RAMB4_S8_S8 double_scan_ram (\r
\r
.CLKA(I_CLK_1),\r
.ADDRA(Hpos_in),\r
.DOA(),\r
.DIA(rgb_in),\r
.WEA(1'b1),\r
.ENA(1'b1),\r
.RSTA(1'b0),\r
\r
.CLKB(I_CLK_2),\r
.ADDRB(Hpos_out),\r
.DOB(rgb_out),\r
.DIB(4'h0),\r
.WEB(1'b0),\r
.ENB(1'b1),\r
.RSTB(1'b0)\r
\r
);\r
`endif\r
//---------------------------------------------------------------------------\r
// vsync remake\r
//\r
// 1 HSYNC_IN delay & HSYNC pulse width = 4xHSYNC(in)\r
//---------------------------------------------------------------------------\r
\r
reg    [2:0]vs_cnt;\r
reg    O_Vsync;\r
\r
always @(posedge O_Hsync)\r
begin\r
   if(~I_V_SYNC)begin\r
      vs_cnt  <= VS_WIDTH-1;\r
   end\r
   else begin\r
      if(vs_cnt==0) vs_cnt <= vs_cnt;\r
      else          vs_cnt <= vs_cnt-1;\r
   end\r
end\r
always @(posedge O_Hsync)\r
begin\r
   case(vs_cnt)\r
      VS_WIDTH-2 :O_Vsync <= 1;\r
	  0          :O_Vsync <= 0;\r
   endcase\r
end\r
//---------------------------------------------------------------------------\r
// output\r
//---------------------------------------------------------------------------\r
\r
assign O_R = rgb_out[7:5]; \r
assign O_G = rgb_out[4:2];\r
assign O_B = rgb_out[1:0]; \r
\r
// converted  H V SYNC\r
assign O_H_SYNCn = ~O_Hsync;\r
assign O_V_SYNCn = ~O_Vsync;\r
\r
endmodule\r
\r
`ifdef DEVICE_CYCLONE\r
module alt_ram_512_8_d (\r
	data_a,\r
	wren_a,\r
	address_a,\r
	data_b,\r
	address_b,\r
	wren_b,\r
	clock_a,\r
	enable_a,\r
	clock_b,\r
	enable_b,\r
	aclr_a,\r
	aclr_b,\r
	q_a,\r
	q_b);\r
\r
	input	[7:0]  data_a;\r
	input	  wren_a;\r
	input	[8:0]  address_a;\r
	input	[7:0]  data_b;\r
	input	[8:0]  address_b;\r
	input	  wren_b;\r
	input	  clock_a;\r
	input	  enable_a;\r
	input	  clock_b;\r
	input	  enable_b;\r
	input	  aclr_a;\r
	input	  aclr_b;\r
	output	[7:0]  q_a;\r
	output	[7:0]  q_b;\r
\r
	wire [7:0] sub_wire0;\r
	wire [7:0] sub_wire1;\r
	wire [7:0] q_a = sub_wire0[7:0];\r
	wire [7:0] q_b = sub_wire1[7:0];\r
\r
	altsyncram	altsyncram_component (\r
				.clocken0 (enable_a),\r
				.clocken1 (enable_b),\r
				.wren_a (wren_a),\r
				.aclr0 (aclr_a),\r
				.clock0 (clock_a),\r
				.wren_b (wren_b),\r
				.aclr1 (aclr_b),\r
				.clock1 (clock_b),\r
				.address_a (address_a),\r
				.address_b (address_b),\r
				.data_a (data_a),\r
				.data_b (data_b),\r
				.q_a (sub_wire0),\r
				.q_b (sub_wire1));\r
	defparam\r
		altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",\r
		altsyncram_component.width_a = 8,\r
		altsyncram_component.widthad_a = 9,\r
		altsyncram_component.numwords_a = 512,\r
		altsyncram_component.width_b = 8,\r
		altsyncram_component.widthad_b = 9,\r
		altsyncram_component.numwords_b = 512,\r
		altsyncram_component.lpm_type = "altsyncram",\r
		altsyncram_component.width_byteena_a = 1,\r
		altsyncram_component.width_byteena_b = 1,\r
		altsyncram_component.outdata_reg_a = "UNREGISTERED",\r
		altsyncram_component.outdata_aclr_a = "NONE",\r
		altsyncram_component.outdata_reg_b = "UNREGISTERED",\r
		altsyncram_component.indata_aclr_a = "CLEAR0",\r
		altsyncram_component.wrcontrol_aclr_a = "CLEAR0",\r
		altsyncram_component.address_aclr_a = "CLEAR0",\r
		altsyncram_component.indata_reg_b = "CLOCK1",\r
		altsyncram_component.address_reg_b = "CLOCK1",\r
		altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1",\r
		altsyncram_component.indata_aclr_b = "CLEAR1",\r
		altsyncram_component.wrcontrol_aclr_b = "CLEAR1",\r
		altsyncram_component.address_aclr_b = "CLEAR1",\r
		altsyncram_component.outdata_aclr_b = "NONE",\r
		altsyncram_component.ram_block_type = "M4K",\r
		altsyncram_component.intended_device_family = "Stratix";\r
\r
\r
endmodule\r
`endif\r
Commit	Line	Data
782690d0 MG	1	//===============================================================================\r
	2	// FPGA VGA INTERFACE FOR ALTERA CYCLONE & XILINX SPARTAN2E\r
	3	//\r
	4	// Version : 2.00\r
	5	//\r
	6	// Copyright(c) 2003 - 2004 Katsumi Degawa , All rights reserved\r
	7	//\r
	8	// based on a design by Tatsuyuki Satoh\r
	9	//\r
	10	// Important !\r
	11	//\r
	12	// This program is freeware for non-commercial use. \r
	13	// An author does no guarantee about this program.\r
	14	// You can use this under your own risk.\r
	15	//\r
	16	// 2004- 9-18 added SPARTAN2E DEVIDE . K.DEGAWA\r
	17	//================================================================================\r
	18	`include "src/mc_conf.v"\r
	19	\r
	20	module mc_vga_if(\r
	21	\r
	22	I_CLK_1,\r
	23	I_CLK_2,\r
	24	I_R,\r
	25	I_G,\r
	26	I_B,\r
	27	I_H_SYNC,\r
	28	I_V_SYNC,\r
	29	\r
	30	O_R,\r
	31	O_G,\r
	32	O_B,\r
	33	O_H_SYNCn,\r
	34	O_V_SYNCn\r
	35	\r
	36	);\r
	37	\r
	38	// input signals\r
	39	input I_CLK_1; // 6.144MHz input pixel clock\r
	40	input I_CLK_2; // 12.288Mhz output pixel clock\r
	41	input [2:0]I_R; // R in\r
	42	input [2:0]I_G; // G in\r
	43	input [1:0]I_B; // B in\r
	44	input I_H_SYNC; // HSYNC input (16KHz)\r
	45	input I_V_SYNC; // VSYNC input (60Hz)\r
	46	\r
	47	// output signals\r
0840cca6 MG	48	output [2:0]O_R; // R out\r
	49	output [2:0]O_G; // G out\r
	50	output [1:0]O_B; // B out\r
782690d0 MG	51	output O_H_SYNCn; // HSYNC output\r
	52	output O_V_SYNCn; // VSYNC output\r
	53	\r
	54	//---------------------------------------------------------------------------\r
	55	// setup parameter\r
	56	//---------------------------------------------------------------------------\r
	57	\r
	58	parameter H_COUNT = 384; // number of pixels in H-SCAN\r
	59	parameter HS_POS = 16; // HSYNC position \r
	60	parameter HS_WIDTH = HS_POS+8; // HSYNC width / pixel\r
	61	parameter VS_WIDTH = 8; // VSYNC width / HSYNC_OUT\r
	62	\r
	63	//---------------------------------------------------------------------------\r
	64	// input timming\r
	65	//---------------------------------------------------------------------------\r
	66	reg [8:0]Hpos_in; // input capture postion\r
	67	reg L_Hsync_i;\r
	68	wire HP_in = ~L_Hsync_i & I_H_SYNC;\r
	69	always@(posedge I_CLK_1)\r
	70	begin\r
	71	Hpos_in <= HP_in ? 0: Hpos_in + 1;\r
	72	L_Hsync_i <= I_H_SYNC;\r
	73	end\r
	74	\r
	75	//---------------------------------------------------------------------------\r
	76	//output timming\r
	77	//---------------------------------------------------------------------------\r
	78	reg [8:0]Hpos_out;\r
	79	reg L_Hsync_o;\r
	80	wire HP_out = ~L_Hsync_o & I_H_SYNC;\r
	81	wire HP_ret = HP_out \| (Hpos_out == H_COUNT-1);\r
	82	\r
	83	always@(posedge I_CLK_2)\r
	84	begin\r
	85	Hpos_out <= HP_ret ? 0:Hpos_out + 1;\r
	86	L_Hsync_o <= I_H_SYNC;\r
	87	end\r
	88	\r
	89	reg O_Hsync;\r
	90	always@(posedge I_CLK_2)\r
	91	begin\r
	92	case(Hpos_out)\r
	93	HS_POS :O_Hsync <= 1'b1;\r
	94	HS_WIDTH:O_Hsync <= 1'b0;\r
	95	default :;\r
	96	endcase\r
	97	end\r
	98	\r
	99	//---------------------------------------------------------------------------\r
	100	// RGB capture(portA) & output(portB)\r
	101	//---------------------------------------------------------------------------\r
	102	wire [7:0]rgb_in = {I_R,I_G,I_B}; // RGB input\r
	103	wire [7:0]rgb_out; // RGB output\r
	104	\r
	105	`ifdef DEVICE_CYCLONE\r
	106	alt_ram_512_8_d double_scan_ram(\r
	107	\r
	108	.clock_a(I_CLK_1),\r
	109	.address_a(Hpos_in),\r
	110	.q_a(),\r
	111	.data_a(rgb_in),\r
	112	.wren_a(1'b1),\r
	113	.enable_a(1'b1),\r
	114	.aclr_a(1'b0),\r
115	\r
116	.clock_b(I_CLK_2),\r
117	.address_b(Hpos_out),\r
118	.q_b(rgb_out),\r
119	.data_b(4'h0),\r
120	.wren_b(1'b0),\r
121	.enable_b(1'b1),\r
122	.aclr_b(1'b0)\r
123	\r
124	);\r
125	`endif\r
126	`ifdef DEVICE_SPARTAN2E\r
127	RAMB4_S8_S8 double_scan_ram (\r
128	\r
129	.CLKA(I_CLK_1),\r
130	.ADDRA(Hpos_in),\r
131	.DOA(),\r
132	.DIA(rgb_in),\r
133	.WEA(1'b1),\r
134	.ENA(1'b1),\r
135	.RSTA(1'b0),\r
136	\r
137	.CLKB(I_CLK_2),\r
138	.ADDRB(Hpos_out),\r
139	.DOB(rgb_out),\r
140	.DIB(4'h0),\r
141	.WEB(1'b0),\r
142	.ENB(1'b1),\r
143	.RSTB(1'b0)\r
144	\r
145	);\r
146	`endif\r
147	//---------------------------------------------------------------------------\r
148	// vsync remake\r
149	//\r
150	// 1 HSYNC_IN delay & HSYNC pulse width = 4xHSYNC(in)\r
151	//---------------------------------------------------------------------------\r
152	\r
153	reg [2:0]vs_cnt;\r
154	reg O_Vsync;\r
155	\r
156	always @(posedge O_Hsync)\r
157	begin\r
158	if(~I_V_SYNC)begin\r
159	vs_cnt <= VS_WIDTH-1;\r
160	end\r
161	else begin\r
162	if(vs_cnt==0) vs_cnt <= vs_cnt;\r
163	else vs_cnt <= vs_cnt-1;\r
164	end\r
165	end\r
166	always @(posedge O_Hsync)\r
167	begin\r
168	case(vs_cnt)\r
169	VS_WIDTH-2 :O_Vsync <= 1;\r
170	0 :O_Vsync <= 0;\r
171	endcase\r
172	end\r
173	//---------------------------------------------------------------------------\r
174	// output\r
175	//---------------------------------------------------------------------------\r
176	\r
0840cca6 MG	177	assign O_R = rgb_out[7:5]; \r
	178	assign O_G = rgb_out[4:2];\r
	179	assign O_B = rgb_out[1:0]; \r
782690d0 MG	180	\r
	181	// converted H V SYNC\r
	182	assign O_H_SYNCn = ~O_Hsync;\r
	183	assign O_V_SYNCn = ~O_Vsync;\r
	184	\r
	185	endmodule\r
	186	\r
	187	`ifdef DEVICE_CYCLONE\r
	188	module alt_ram_512_8_d (\r
	189	data_a,\r
	190	wren_a,\r
	191	address_a,\r
	192	data_b,\r
	193	address_b,\r
	194	wren_b,\r
	195	clock_a,\r
	196	enable_a,\r
	197	clock_b,\r
	198	enable_b,\r
	199	aclr_a,\r
	200	aclr_b,\r
	201	q_a,\r
	202	q_b);\r
	203	\r
	204	input [7:0] data_a;\r
	205	input wren_a;\r
	206	input [8:0] address_a;\r
	207	input [7:0] data_b;\r
	208	input [8:0] address_b;\r
	209	input wren_b;\r
	210	input clock_a;\r
	211	input enable_a;\r
	212	input clock_b;\r
	213	input enable_b;\r
	214	input aclr_a;\r
	215	input aclr_b;\r
	216	output [7:0] q_a;\r
	217	output [7:0] q_b;\r
	218	\r
	219	wire [7:0] sub_wire0;\r
	220	wire [7:0] sub_wire1;\r
	221	wire [7:0] q_a = sub_wire0[7:0];\r
	222	wire [7:0] q_b = sub_wire1[7:0];\r
	223	\r
	224	altsyncram altsyncram_component (\r
	225	.clocken0 (enable_a),\r
	226	.clocken1 (enable_b),\r
	227	.wren_a (wren_a),\r
	228	.aclr0 (aclr_a),\r
	229	.clock0 (clock_a),\r
	230	.wren_b (wren_b),\r
	231	.aclr1 (aclr_b),\r
	232	.clock1 (clock_b),\r
	233	.address_a (address_a),\r
	234	.address_b (address_b),\r
	235	.data_a (data_a),\r
	236	.data_b (data_b),\r
	237	.q_a (sub_wire0),\r
	238	.q_b (sub_wire1));\r
	239	defparam\r
	240	altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",\r
	241	altsyncram_component.width_a = 8,\r
	242	altsyncram_component.widthad_a = 9,\r
	243	altsyncram_component.numwords_a = 512,\r
244	altsyncram_component.width_b = 8,\r
245	altsyncram_component.widthad_b = 9,\r
246	altsyncram_component.numwords_b = 512,\r
247	altsyncram_component.lpm_type = "altsyncram",\r
248	altsyncram_component.width_byteena_a = 1,\r
249	altsyncram_component.width_byteena_b = 1,\r
250	altsyncram_component.outdata_reg_a = "UNREGISTERED",\r
251	altsyncram_component.outdata_aclr_a = "NONE",\r
252	altsyncram_component.outdata_reg_b = "UNREGISTERED",\r
253	altsyncram_component.indata_aclr_a = "CLEAR0",\r
254	altsyncram_component.wrcontrol_aclr_a = "CLEAR0",\r
255	altsyncram_component.address_aclr_a = "CLEAR0",\r
256	altsyncram_component.indata_reg_b = "CLOCK1",\r
257	altsyncram_component.address_reg_b = "CLOCK1",\r
258	altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1",\r
259	altsyncram_component.indata_aclr_b = "CLEAR1",\r
260	altsyncram_component.wrcontrol_aclr_b = "CLEAR1",\r
261	altsyncram_component.address_aclr_b = "CLEAR1",\r
262	altsyncram_component.outdata_aclr_b = "NONE",\r
263	altsyncram_component.ram_block_type = "M4K",\r
264	altsyncram_component.intended_device_family = "Stratix";\r
265	\r
266	\r
267	endmodule\r
268	`endif\r