we have no sound rom
[fpga-games] / galaxian / src / mc_video.v
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1//===============================================================================\r
2// FPGA GALAXIAN VIDEO\r
3//\r
4// Version : 2.50\r
5//\r
6// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
7//\r
8// Important !\r
9//\r
10// This program is freeware for non-commercial use. \r
11// An author does no guarantee about this program.\r
12// You can use this under your own risk.\r
13//\r
14// 2004- 4-30 galaxian modify by K.DEGAWA\r
15// 2004- 5- 6 first release.\r
16// 2004- 8-23 Improvement with T80-IP.\r
17// 2004- 9-22 The problem which missile didn't sometimes come out from was improved.\r
18//================================================================================\r
19//-----------------------------------------------------------------------------------------\r
20// H_CNT[0],H_CNT[1],H_CNT[2],H_CNT[3],H_CNT[4],H_CNT[5],H_CNT[6],H_CNT[7],H_CNT[8], \r
21// 1 H 2 H 4H 8H 16 H 32H 64 H 128 H 256 H\r
22//-----------------------------------------------------------------------------------------\r
23// V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7] \r
24// 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V \r
25//-----------------------------------------------------------------------------------------\r
26\r
27module mc_video(\r
28\r
29I_CLK_18M,\r
30I_CLK_12M,\r
31I_CLK_6M,\r
32I_H_CNT,\r
33I_V_CNT,\r
34I_H_FLIP,\r
35I_V_FLIP,\r
36I_V_BLn,\r
37I_C_BLn,\r
38\r
39I_A,\r
40I_OBJ_SUB_A,\r
41I_BD,\r
42I_OBJ_RAM_RQn,\r
43I_OBJ_RAM_RDn,\r
44I_OBJ_RAM_WRn,\r
45I_VID_RAM_RDn,\r
46I_VID_RAM_WRn,\r
47\r
48O_OBJ_ROM_A,\r
49I_OBJ_ROM_A_D,\r
50I_OBJ_ROM_B_D,\r
51\r
52O_C_BLnX,\r
53O_8HF,\r
54O_256HnX,\r
55O_1VF,\r
56O_MISSILEn,\r
57O_SHELLn,\r
58O_BD,\r
59O_VID,\r
60O_COL\r
61\r
62);\r
63\r
64input I_CLK_18M;\r
65input I_CLK_12M;\r
66input I_CLK_6M;\r
67input [8:0]I_H_CNT;\r
68input [7:0]I_V_CNT;\r
69input I_H_FLIP;\r
70input I_V_FLIP;\r
71input I_V_BLn;\r
72input I_C_BLn;\r
73\r
74input [9:0]I_A;\r
75input [7:0]I_BD;\r
76input [2:0]I_OBJ_SUB_A;\r
77input I_OBJ_RAM_RQn;\r
78input I_OBJ_RAM_RDn;\r
79input I_OBJ_RAM_WRn;\r
80input I_VID_RAM_RDn;\r
81input I_VID_RAM_WRn;\r
82\r
83output [10:0]O_OBJ_ROM_A;\r
84input [7:0]I_OBJ_ROM_A_D;\r
85input [7:0]I_OBJ_ROM_B_D;\r
86\r
87output O_C_BLnX;\r
88output O_8HF;\r
89output O_256HnX;\r
90output O_1VF;\r
91output O_MISSILEn;\r
92output O_SHELLn;\r
93\r
94output [7:0]O_BD;\r
95output [1:0]O_VID;\r
96output [2:0]O_COL;\r
97\r
98wire WB_LDn;\r
99wire WB_CNTRLDn;\r
100wire WB_CNTRCLRn;\r
101wire WB_COLLn;\r
102wire WB_VPLn;\r
103wire WB_OBJDATALn;\r
104wire WB_MLDn;\r
105wire WB_SLDn;\r
106wire W_3D;\r
107reg W_LDn;\r
108reg W_CNTRLDn;\r
109reg W_CNTRCLRn;\r
110reg W_COLLn;\r
111reg W_VPLn;\r
112reg W_OBJDATALn;\r
113reg W_MLDn;\r
114reg W_SLDn;\r
115\r
116always@(negedge I_CLK_12M)\r
117begin\r
118 W_LDn <= WB_LDn;\r
119 W_CNTRLDn <= WB_CNTRLDn;\r
120 W_CNTRCLRn <= WB_CNTRCLRn;\r
121 W_COLLn <= WB_COLLn;\r
122 W_VPLn <= WB_VPLn;\r
123 W_OBJDATALn <= WB_OBJDATALn;\r
124 W_MLDn <= WB_MLDn;\r
125 W_SLDn <= WB_SLDn;\r
126end\r
127\r
128mc_ld_pls LD_PLS(\r
129\r
130.I_CLK_6M(~I_CLK_6M),\r
131.I_H_CNT(I_H_CNT),\r
132.I_3D_DI(W_3D),\r
133\r
134.O_LDn(WB_LDn),\r
135.O_CNTRLDn(WB_CNTRLDn),\r
136.O_CNTRCLRn(WB_CNTRCLRn),\r
137.O_COLLn(WB_COLLn),\r
138.O_VPLn(WB_VPLn),\r
139.O_OBJDATALn(WB_OBJDATALn),\r
140.O_MLDn(WB_MLDn),\r
141.O_SLDn(WB_SLDn)\r
142\r
143);\r
144\r
145wire W_H_FLIP1 = ~I_H_CNT[8]&I_H_FLIP;\r
146\r
147wire [7:3]W_HF_CNT = I_H_CNT[7:3]^{5{W_H_FLIP1}};\r
148wire [7:0]W_VF_CNT = I_V_CNT[7:0]^{8{I_V_FLIP}};\r
149\r
150assign O_8HF = W_HF_CNT[3];\r
151assign O_1VF = W_VF_CNT[0];\r
152\r
153reg [7:0]W_OBJ_D;\r
154wire [3:0]W_6J_DA = {I_H_FLIP , W_HF_CNT[7],W_HF_CNT[3],I_H_CNT[2]};\r
155wire [3:0]W_6J_DB = {W_OBJ_D[6],W_HF_CNT[3]&I_H_CNT[1], I_H_CNT[2],I_H_CNT[1]};\r
156wire [3:0]W_6J_Q = I_H_CNT[8] ? W_6J_DB:W_6J_DA;\r
157\r
158wire W_H_FLIP2 = W_6J_Q[3];\r
159// Prats 4F,5F\r
160wire [7:0]W_OBJ_RAM_AB = {1'b0,I_H_CNT[8],W_6J_Q[2],W_HF_CNT[6:4],W_6J_Q[1:0]};\r
161wire [7:0]W_OBJ_RAM_A = I_OBJ_RAM_RQn ? W_OBJ_RAM_AB: I_A[7:0] ;\r
162\r
163wire [7:0]W_OBJ_RAM_DOA,W_OBJ_RAM_DOB;\r
164\r
165reg [7:0]W_H_POSI;\r
166always@(posedge I_CLK_12M) W_H_POSI <= W_OBJ_RAM_DOB;\r
167\r
168mc_obj_ram OBJ_RAM(\r
169\r
170.I_CLKA(I_CLK_12M),\r
171.I_ADDRA(I_A[7:0]),\r
172.I_WEA(~I_OBJ_RAM_WRn),\r
173.I_CEA(~I_OBJ_RAM_RQn),\r
174.I_DA(I_BD),\r
175.O_DA(W_OBJ_RAM_DOA),\r
176\r
177.I_CLKB(I_CLK_12M),\r
178.I_ADDRB(W_OBJ_RAM_AB),\r
179.I_WEB(1'b0),\r
180.I_CEB(1'b1),\r
181.I_DB(8'h00),\r
182.O_DB(W_OBJ_RAM_DOB)\r
183\r
184);\r
185\r
186wire [7:0]W_OBJ_RAM_D = I_OBJ_RAM_RDn ? 8'h00: W_OBJ_RAM_DOA;\r
187// Prats 4L\r
188always@(posedge W_OBJDATALn) W_OBJ_D <= W_H_POSI; \r
189// Prats 4,5N\r
190\r
191wire [8:0]W_45N_Q = W_VF_CNT[7:0] + W_H_POSI ;\r
192assign W_3D = ~(&W_45N_Q[7:0]); \r
193\r
194reg [7:0]W_2M_Q;\r
195always@(posedge W_VPLn or negedge I_V_BLn)\r
196begin\r
197 if(I_V_BLn==1'b0)\r
198 W_2M_Q <= 0;\r
199 else\r
200 W_2M_Q <= W_45N_Q[7:0];\r
201end\r
202\r
203wire W_2N = I_H_CNT[8]&W_OBJ_D[7];\r
204wire [3:0]W_1M = W_2M_Q[3:0]^{W_2N,W_2N,W_2N,W_2N};\r
205\r
206wire W_VID_RAM_CSn = I_VID_RAM_RDn & I_VID_RAM_WRn;\r
207\r
208wire [7:0]W_VID_RAM_DI = I_VID_RAM_WRn ? 8'h00 : I_BD ;\r
209wire [7:0]W_VID_RAM_DOA;\r
210\r
211wire [11:0]W_VID_RAM_AA = {~(&W_2M_Q[7:4]),W_VID_RAM_CSn, 10'h00 /*I_A[9:0]*/};\r
212wire [11:0]W_VID_RAM_AB = { 1'b0, 1'b0,W_2M_Q[7:4],W_1M[3],W_HF_CNT[7:3]};\r
213\r
214wire [11:0]W_VID_RAM_A = I_C_BLn ? W_VID_RAM_AB:W_VID_RAM_AA;\r
215\r
216wire [7:0]W_VID_RAM_D = I_VID_RAM_RDn ? 8'h00 :W_VID_RAM_DOA;\r
217\r
218wire [7:0]W_VID_RAM_DOB;\r
219\r
220mc_vid_ram VID_RAM(\r
221\r
222.I_CLKA(I_CLK_12M),\r
223.I_ADDRA(I_A[9:0]),\r
224.I_DA(W_VID_RAM_DI),\r
225.I_WEA(~I_VID_RAM_WRn),\r
226.I_CEA(~W_VID_RAM_CSn),\r
227.O_DA(W_VID_RAM_DOA),\r
228\r
229.I_CLKB(I_CLK_12M),\r
230.I_ADDRB(W_VID_RAM_A[9:0]),\r
231.I_DB(8'h00),\r
232.I_WEB(1'b0),\r
233.I_CEB(1'b1),\r
234.O_DB(W_VID_RAM_DOB)\r
235\r
236);\r
237//-- VIDEO DATA OUTPUT --------------\r
238assign O_BD = W_OBJ_RAM_D | W_VID_RAM_D;\r
239\r
240wire W_SRLD = ~(W_LDn | W_VID_RAM_A[11]);\r
241\r
242wire [7:0]W_OBJ_ROM_AB = {W_OBJ_D[5:0],W_1M[3],W_OBJ_D[6]^I_H_CNT[3]};\r
243\r
244wire [7:0]W_OBJ_ROM_A = I_H_CNT[8] ? W_OBJ_ROM_AB: W_VID_RAM_DOB;\r
245\r
246assign O_OBJ_ROM_A = {W_OBJ_ROM_A,W_1M[2:0]};\r
247\r
248wire [7:0]W_1K_D = I_OBJ_ROM_A_D;\r
249wire [7:0]W_1H_D = I_OBJ_ROM_B_D;\r
250\r
251//---------------------------------------------------------------------------------\r
252wire W_2L_Qa,W_2K_Qd;\r
253wire W_2J_Qa,W_2H_Qd;\r
254wire W_H_FLIP2X;\r
255\r
256wire [3:0]W_3L_A = {W_2J_Qa,W_2L_Qa, 1'b1,W_SRLD};\r
257wire [3:0]W_3L_B = {W_2H_Qd,W_2K_Qd,W_SRLD, 1'b1}; \r
258wire [3:0]W_3L_Y = W_H_FLIP2X ? W_3L_B: W_3L_A; // [3]=RAW1,[2]=RAW0\r
259\r
260wire W_RAW0 = W_3L_Y[2];\r
261wire W_RAW1 = W_3L_Y[3];\r
262\r
263wire W_SRCLK = I_CLK_6M;\r
264//------ PARTS 2KL ---------------------------------------------- \r
265wire [1:0]C_2KL = W_3L_Y[1:0];\r
266wire [7:0]I_2KL = W_1K_D;\r
267reg [7:0]reg_2KL;\r
268\r
269assign W_2L_Qa = reg_2KL[7];\r
270assign W_2K_Qd = reg_2KL[0];\r
271always@(posedge W_SRCLK)\r
272begin\r
273 case(C_2KL)\r
274 2'b00: reg_2KL <= reg_2KL;\r
275 2'b10: reg_2KL <= {reg_2KL[6:0],1'b0};\r
276 2'b01: reg_2KL <= {1'b0,reg_2KL[7:1]};\r
277 2'b11: reg_2KL <= I_2KL;\r
278 endcase\r
279end\r
280//------ PARTS 2HJ ---------------------------------------------- \r
281wire [1:0]C_2HJ = W_3L_Y[1:0];\r
282wire [7:0]I_2HJ = W_1H_D;\r
283reg [7:0]reg_2HJ;\r
284\r
285assign W_2J_Qa = reg_2HJ[7];\r
286assign W_2H_Qd = reg_2HJ[0];\r
287always@(posedge W_SRCLK)\r
288begin\r
289 case(C_2HJ)\r
290 2'b00: reg_2HJ <= reg_2HJ;\r
291 2'b10: reg_2HJ <= {reg_2HJ[6:0],1'b0};\r
292 2'b01: reg_2HJ <= {1'b0,reg_2HJ[7:1]};\r
293 2'b11: reg_2HJ <= I_2HJ;\r
294 endcase\r
295end\r
296\r
297//----- SHT2 -----------------------------------------------------\r
298// Prats 6K\r
299reg [2:0]W_6K_Q;\r
300always@(posedge W_COLLn) W_6K_Q <= W_H_POSI[2:0];\r
301\r
302// Prats 6P\r
303reg [6:0]W_6P_Q;\r
304always@(posedge I_CLK_6M)\r
305begin\r
306 if(W_LDn==1'b0) W_6P_Q <= {W_H_FLIP2,W_H_FLIP1,I_C_BLn,~I_H_CNT[8],W_6K_Q[2:0]};\r
307 else W_6P_Q <= W_6P_Q;\r
308end\r
309\r
310assign W_H_FLIP2X = W_6P_Q[6];\r
311wire W_H_FLIP1X = W_6P_Q[5];\r
312wire W_C_BLnX = W_6P_Q[4];\r
313wire W_256HnX = W_6P_Q[3];\r
314wire [2:0]W_CD = W_6P_Q[2:0];\r
315\r
316assign O_256HnX = W_256HnX;\r
317assign O_C_BLnX = W_C_BLnX;\r
318\r
319wire W_45T_CLR = W_CNTRCLRn | W_256HnX ;\r
320reg [7:0]W_45T_Q;\r
321\r
322always@(posedge I_CLK_6M)\r
323begin\r
324 if(W_45T_CLR==1'b0)\r
325 W_45T_Q <= 0;\r
326 else if(W_CNTRLDn==1'b0)\r
327 W_45T_Q <= W_H_POSI;\r
328 else\r
329 W_45T_Q <= W_45T_Q + 1;\r
330end\r
331\r
332wire [7:0]W_LRAM_A = W_45T_Q^{8{W_H_FLIP1X}};\r
333wire W_LRAM_WE = ~I_CLK_6M;\r
334\r
335wire [4:0]W_LRAM_DI;\r
336wire [4:0]W_LRAM_DO;\r
337\r
338reg [1:0]W_RV;\r
339reg [2:0]W_RC;\r
340wire W_1U_CLK = ~I_CLK_6M;\r
341\r
342always@(posedge W_1U_CLK)\r
343begin\r
344 W_RV <= W_LRAM_DO[1:0]; \r
345 W_RC <= W_LRAM_DO[4:2];\r
346end\r
347\r
348wire W_LRAM_AND = ~(~((W_LRAM_A[4]|W_LRAM_A[5])|(W_LRAM_A[6]|W_LRAM_A[7]))|W_256HnX );\r
349wire W_RAW_OR = W_RAW0 | W_RAW1 ;\r
350\r
351wire [1:0]W_VID;\r
352wire [2:0]W_COL;\r
353\r
354assign W_VID[0] = ~(~(W_RAW0&W_RV[1])&W_RV[0]);\r
355assign W_VID[1] = ~(~(W_RAW1&W_RV[0])&W_RV[1]);\r
356assign W_COL[0] = ~(~(W_RAW_OR&W_CD[0]&W_RC[1]&W_RC[2])&W_RC[0]);\r
357assign W_COL[1] = ~(~(W_RAW_OR&W_CD[1]&W_RC[2]&W_RC[0])&W_RC[1]);\r
358assign W_COL[2] = ~(~(W_RAW_OR&W_CD[2]&W_RC[0]&W_RC[1])&W_RC[2]);\r
359\r
360assign O_VID = W_VID;\r
361assign O_COL = W_COL;\r
362\r
363assign W_LRAM_DI[0] = W_LRAM_AND&W_VID[0];\r
364assign W_LRAM_DI[1] = W_LRAM_AND&W_VID[1]; \r
365assign W_LRAM_DI[2] = W_LRAM_AND&W_COL[0];\r
366assign W_LRAM_DI[3] = W_LRAM_AND&W_COL[1];\r
367assign W_LRAM_DI[4] = W_LRAM_AND&W_COL[2];\r
368\r
369mc_lram LRAM(\r
370\r
371.I_CLK(I_CLK_18M),\r
372.I_ADDR(W_LRAM_A),\r
373.I_WE(W_LRAM_WE),\r
374.I_D(W_LRAM_DI),\r
375.O_Dn(W_LRAM_DO)\r
376\r
377);\r
378\r
379mc_missile MISSILE(\r
380\r
381.I_CLK_18M(I_CLK_18M),\r
382.I_CLK_6M(I_CLK_6M),\r
383.I_C_BLn_X(W_C_BLnX),\r
384.I_MLDn(W_MLDn),\r
385.I_SLDn(W_SLDn),\r
386.I_HPOS(W_H_POSI),\r
387\r
388.O_MISSILEn(O_MISSILEn),\r
389.O_SHELLn(O_SHELLn)\r
390\r
391);\r
392\r
393endmodule\r
394\r
395\r
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