only start running, when the dcm is locked
[fpga-games] / galaxian / src / mc_clock.v
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1//---------------------------------------------------------------------\r
2// FPGA MOONCRESTA CLOCK GEN \r
3//\r
4// Version : 1.00\r
5//\r
6// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
7//\r
8// Important !\r
9//\r
10// This program is freeware for non-commercial use. \r
11// An author does no guarantee about this program.\r
12// You can use this under your own risk.\r
13//\r
14//---------------------------------------------------------------------\r
15\r
16\r
17\r
18module mc_clock(\r
19\r
c3bcc38a 20I_CLK_36M,\r
fb335bc2 21I_DCM_LOCKED,\r
c3bcc38a 22O_CLK_18M,\r
782690d0 23O_CLK_12M,\r
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24O_CLK_06M,\r
25O_CLK_06Mn\r
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26\r
27);\r
28\r
c3bcc38a 29input I_CLK_36M;\r
fb335bc2 30input I_DCM_LOCKED;\r
c3bcc38a 31output O_CLK_18M;\r
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32output O_CLK_12M;\r
33output O_CLK_06M;\r
4b3ff7d8 34output O_CLK_06Mn;\r
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35\r
36// 2/3 clock divider(duty 33%)\r
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37//I_CLK 1010101010101010101\r
38//c_ff10 0011110011110011110\r
39//c_ff11 0011000011000011000\r
40//c_ff20 0000110000110000110\r
41//c_ff21 0110000110000110000\r
42//O_12M 0000110110110110110\r
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43reg [1:0] state;\r
44reg clk_12m;\r
45initial state = 0;\r
46initial clk_12m = 0;\r
47\r
48// 2/3 clock (duty 66%)\r
0a770302 49always @(posedge I_CLK_36M)\r
782690d0 50begin\r
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51 if (I_DCM_LOCKED == 1) begin\r
52 case (state)\r
53 2'd0: state <= 2'd1;\r
54 2'd1: state <= 2'd2;\r
55 2'd2: state <= 2'd0;\r
56 2'd3: state <= 2'd0;\r
57 endcase\r
c3bcc38a 58\r
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59 if (state == 2'd2)\r
60 clk_12m = 0;\r
61 else\r
62 clk_12m = 1;\r
63 end\r
64 else begin\r
65 state <= 2'd0;\r
c3bcc38a 66 clk_12m = 0;\r
fb335bc2 67 end\r
782690d0 68end\r
782690d0 69\r
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70assign O_CLK_12M = clk_12m;\r
71\r
72reg CLK_18M;\r
73always @(posedge I_CLK_36M)\r
74begin\r
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75 if (I_DCM_LOCKED == 1)\r
76 CLK_18M <= ~ CLK_18M;\r
77 else\r
78 CLK_18M <= 0;\r
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79end\r
80assign O_CLK_18M = CLK_18M;\r
81\r
782690d0 82// 1/3 clock divider (duty 50%)\r
c3bcc38a 83reg CLK_6M;\r
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84reg CLK_6Mn;\r
85\r
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86always @(posedge O_CLK_12M)\r
87begin\r
782690d0 88 CLK_6M <= ~CLK_6M;\r
4b3ff7d8 89 CLK_6Mn <= CLK_6M;\r
782690d0 90end\r
4b3ff7d8 91\r
782690d0 92assign O_CLK_06M = CLK_6M;\r
4b3ff7d8 93assign O_CLK_06Mn = CLK_6Mn;\r
782690d0 94\r
c3bcc38a 95endmodule\r
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