only start running, when the dcm is locked
[fpga-games] / galaxian / src / mc_top.v
CommitLineData
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1//===============================================================================\r
2// FPGA GALAXIAN TOP\r
3//\r
4// Version : 2.50\r
5//\r
6// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
7//\r
8// Important !\r
9//\r
10// This program is freeware for non-commercial use. \r
11// An author does no guarantee about this program.\r
12// You can use this under your own risk.\r
13//\r
14// 2004- 4-30 galaxian modify by K.DEGAWA\r
15// 2004- 5- 6 first release.\r
16// 2004- 8-23 Improvement with T80-IP.\r
17// 2004- 9-18 The description of ALTERA(CYCLONE) and XILINX(SPARTAN2E) was made one.\r
18// 2004- 9-22 The problem which missile didn't sometimes come out from was improved.\r
19//================================================================================\r
20\r
21`include "src/mc_conf.v" \r
22 \r
23module mc_top(\r
24\r
25// FPGA_USE\r
26I_CLK_125M,\r
27\r
28`ifdef PSPAD_USE\r
29// PS_PAD interface\r
30psCLK,\r
31psSEL,\r
32psTXD,\r
33psRXD,\r
34`endif\r
35\r
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36// INPORT SW IF\r
37I_PSW,\r
38\r
39// SOUND OUT\r
40O_SOUND_OUT_L,\r
41O_SOUND_OUT_R,\r
42\r
43// VGA (VIDEO) IF\r
44O_VGA_R,\r
45O_VGA_G,\r
46O_VGA_B,\r
47O_VGA_H_SYNCn,\r
48O_VGA_V_SYNCn\r
49\r
50);\r
51\r
52// FPGA_USE\r
53input I_CLK_125M;\r
54\r
55// CPU ADDRESS BUS\r
56wire [15:0]W_A;\r
57// CPU IF\r
58wire W_CPU_RDn;\r
59wire W_CPU_WRn;\r
60wire W_CPU_MREQn;\r
61wire W_CPU_RFSHn;\r
62wire W_CPU_BUSAKn;\r
63wire W_CPU_IORQn;\r
64wire W_CPU_M1n;\r
65wire W_CPU_CLK;\r
66wire W_CPU_HRDWR_RESETn;\r
67wire W_CPU_WAITn;\r
68wire W_CPU_NMIn;\r
69\r
70`ifdef PSPAD_USE\r
71// PS_PAD interface\r
72input psRXD;\r
73output psTXD,psCLK,psSEL;\r
74`endif\r
75\r
782690d0 76// INPORT SW IF\r
3fc34adf 77input [8:0]I_PSW;\r
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78\r
79// SOUND OUT \r
80output O_SOUND_OUT_L;\r
81output O_SOUND_OUT_R;\r
82\r
83// VGA (VIDEO) IF\r
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84output [3:0]O_VGA_R;\r
85output [3:0]O_VGA_G;\r
86output [3:0]O_VGA_B;\r
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87output O_VGA_H_SYNCn;\r
88output O_VGA_V_SYNCn;\r
89\r
3fc34adf 90wire W_RESETn = |(~I_PSW[8:5]);\r
782690d0 91//------ CLOCK GEN ---------------------------\r
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92wire W_CLK_18M;\r
93wire W_CLK_36M;\r
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94wire W_CLK_12M,WB_CLK_12M;\r
95wire W_CLK_6M,WB_CLK_6M;\r
4b3ff7d8 96wire W_CLK_6Mn;\r
782690d0 97wire W_STARS_CLK;\r
fb335bc2 98wire W_DCM_LOCKED;\r
782690d0 99\r
b884ab49 100mc_dcm clockgen(\r
782690d0 101.CLKIN_IN(I_CLK_125M),\r
fc28fcbf 102.RST_IN(! W_RESETn),\r
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103.CLKFX_OUT(W_CLK_36M),\r
104.LOCKED_OUT(W_DCM_LOCKED)\r
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105);\r
106\r
107//------ H&V COUNTER -------------------------\r
108wire [8:0]W_H_CNT;\r
109wire [7:0]W_V_CNT;\r
110wire W_H_BL;\r
111wire W_V_BLn;\r
112wire W_C_BLn;\r
113wire W_H_SYNC;\r
114wire W_V_SYNC;\r
115\r
116//------ CPU RAM ----------------------------\r
117wire [7:0]W_CPU_RAM_DO;\r
118\r
119//------ ADDRESS DECDER ----------------------\r
120wire W_CPU_ROM_CSn;\r
121wire W_CPU_RAM_RDn;\r
122wire W_CPU_RAM_WRn;\r
123wire W_CPU_RAM_CSn;\r
124wire W_OBJ_RAM_RDn;\r
125wire W_OBJ_RAM_WRn;\r
126wire W_OBJ_RAM_RQn;\r
127wire W_VID_RAM_RDn;\r
128wire W_VID_RAM_WRn;\r
129wire W_SW0_OEn;\r
130wire W_SW1_OEn;\r
131wire W_DIP_OEn;\r
132wire W_WDR_OEn;\r
133wire W_LAMP_WEn;\r
134wire W_SOUND_WEn;\r
135wire W_PITCHn;\r
136wire W_H_FLIP;\r
137wire W_V_FLIP;\r
138wire W_BD_G;\r
139wire W_STARS_ON;\r
140\r
141wire W_VID_RDn = W_OBJ_RAM_RDn & W_VID_RAM_RDn ;\r
142wire W_SW_OEn = W_SW0_OEn & W_SW1_OEn & W_DIP_OEn ;\r
143//------- INPORT -----------------------------\r
144wire [7:0]W_SW_DO;\r
145//------- VIDEO -----------------------------\r
146wire [7:0]W_VID_DO;\r
147//--------------------------------------------\r
148\r
149mc_clock MC_CLK(\r
150\r
c3bcc38a 151.I_CLK_36M(W_CLK_36M),\r
fb335bc2 152.I_DCM_LOCKED(W_DCM_LOCKED),\r
c3bcc38a 153.O_CLK_18M(W_CLK_18M),\r
782690d0 154.O_CLK_12M(WB_CLK_12M),\r
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155.O_CLK_06M(WB_CLK_6M),\r
156.O_CLK_06Mn(W_CLK_6Mn)\r
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157\r
158);\r
159\r
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160assign W_CLK_12M = WB_CLK_12M;\r
161assign W_CLK_6M = WB_CLK_6M;\r
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162//--- DATA I/F -------------------------------------\r
163reg [7:0]W_CPU_ROM_DO;\r
164wire [7:0]W_CPU_ROM_DOB = W_CPU_ROM_CSn ? 8'h00: W_CPU_ROM_DO ;\r
165\r
166wire [7:0]W_BDO = W_SW_DO | W_VID_DO | W_CPU_RAM_DO | W_CPU_ROM_DOB ;\r
167wire [7:0]W_BDI;\r
168\r
169//--- CPU I/F -------------------------------------\r
170reg [3:0]rst_count;\r
171always@(posedge W_H_CNT[0] or negedge W_RESETn)\r
172begin\r
173 if(! W_RESETn) rst_count <= 0;\r
174 else begin\r
175 if( rst_count == 15) \r
176 rst_count <= rst_count;\r
177 else\r
178 rst_count <= rst_count+1;\r
179 end\r
180end\r
181\r
182assign W_CPU_RESETn = W_RESETn;\r
183assign W_CPU_CLK = W_H_CNT[0];\r
184\r
185Z80IP CPU(\r
186 \r
187.CLK(W_CPU_CLK),\r
188.RESET_N(W_CPU_RESETn),\r
189.INT_N(1'b1),\r
190.NMI_N(W_CPU_NMIn),\r
191.ADRS(W_A),\r
192.DOUT(W_BDI),\r
193.DINP(W_BDO),\r
194.M1_N(),\r
195.MREQ_N(W_CPU_MREQn),\r
196.IORQ_N(),\r
197.RD_N(W_CPU_RDn ),\r
198.WR_N(W_CPU_WRn ),\r
199.WAIT_N(W_CPU_WAITn),\r
200.BUSWO(),\r
201.RFSH_N(W_CPU_RFSHn),\r
202.HALT_N()\r
203\r
204);\r
205\r
206wire W_CPU_RAM_CLK = W_CLK_12M & ~W_CPU_RAM_CSn;\r
207\r
208mc_cpu_ram MC_CPU_RAM(\r
209\r
210.I_CLK(W_CPU_RAM_CLK),\r
211.I_ADDR(W_A[9:0]),\r
212.I_D(W_BDI),\r
213.I_WE(~W_CPU_WRn),\r
214.I_OE(~W_CPU_RAM_RDn ),\r
215.O_D(W_CPU_RAM_DO)\r
216\r
217);\r
218\r
219\r
220mc_adec MC_ADEC(\r
221\r
222.I_CLK_12M(W_CLK_12M),\r
223.I_CLK_6M(W_CLK_6M),\r
224.I_CPU_CLK(W_H_CNT[0]),\r
225.I_RSTn(W_RESETn),\r
226\r
227.I_CPU_A(W_A),\r
228.I_CPU_D(W_BDI[0]),\r
229.I_MREQn(W_CPU_MREQn),\r
230.I_RFSHn(W_CPU_RFSHn),\r
231.I_RDn(W_CPU_RDn),\r
232.I_WRn(W_CPU_WRn),\r
233.I_H_BL(W_H_BL),\r
234.I_V_BLn(W_V_BLn),\r
235\r
236.O_WAITn(W_CPU_WAITn),\r
237.O_NMIn(W_CPU_NMIn),\r
238.O_CPU_ROM_CSn(W_CPU_ROM_CSn),\r
239.O_CPU_RAM_RDn(W_CPU_RAM_RDn),\r
240.O_CPU_RAM_WRn(W_CPU_RAM_WRn),\r
241.O_CPU_RAM_CSn(W_CPU_RAM_CSn),\r
242.O_OBJ_RAM_RDn(W_OBJ_RAM_RDn),\r
243.O_OBJ_RAM_WRn(W_OBJ_RAM_WRn),\r
244.O_OBJ_RAM_RQn(W_OBJ_RAM_RQn),\r
245.O_VID_RAM_RDn(W_VID_RAM_RDn),\r
246.O_VID_RAM_WRn(W_VID_RAM_WRn),\r
247.O_SW0_OEn(W_SW0_OEn),\r
248.O_SW1_OEn(W_SW1_OEn),\r
249.O_DIP_OEn(W_DIP_OEn),\r
250.O_WDR_OEn(W_WDR_OEn),\r
251.O_LAMP_WEn(W_LAMP_WEn),\r
252.O_SOUND_WEn(W_SOUND_WEn),\r
253.O_PITCHn(W_PITCHn),\r
254.O_H_FLIP(W_H_FLIP),\r
255.O_V_FLIP(W_V_FLIP),\r
256.O_BD_G(W_BD_G),\r
257.O_STARS_ON(W_STARS_ON)\r
258\r
259);\r
260\r
261//-------- SOUND I/F -----------------------------\r
262//--- Parts 9L ---------\r
263reg [7:0]W_9L_Q;\r
264always@(posedge W_CLK_12M or negedge W_RESETn)\r
265begin\r
266 if(W_RESETn == 1'b0)begin\r
267 W_9L_Q <= 0;\r
268 end \r
269 else begin\r
270 if(W_SOUND_WEn == 1'b0)begin\r
271 case(W_A[2:0])\r
272 3'h0 : W_9L_Q[0] <= W_BDI[0];\r
273 3'h1 : W_9L_Q[1] <= W_BDI[0];\r
274 3'h2 : W_9L_Q[2] <= W_BDI[0];\r
275 3'h3 : W_9L_Q[3] <= W_BDI[0];\r
276 3'h4 : W_9L_Q[4] <= W_BDI[0];\r
277 3'h5 : W_9L_Q[5] <= W_BDI[0];\r
278 3'h6 : W_9L_Q[6] <= W_BDI[0];\r
279 3'h7 : W_9L_Q[7] <= W_BDI[0];\r
280 endcase\r
281 end\r
282 end\r
283end\r
284wire W_VOL1 = W_9L_Q[6];\r
285wire W_VOL2 = W_9L_Q[7];\r
286wire W_FIRE = W_9L_Q[5];\r
287wire W_HIT = W_9L_Q[3];\r
288wire W_FS3 = W_9L_Q[2];\r
289wire W_FS2 = W_9L_Q[1];\r
290wire W_FS1 = W_9L_Q[0];\r
291//---------------------------------------------------\r
292//---- CPU DATA WATCH -------------------------------\r
293wire ZMWR = W_CPU_MREQn | W_CPU_WRn ;\r
294\r
295reg [1:0]on_game;\r
296always @(posedge W_CPU_CLK)\r
297begin\r
298 if(~ZMWR)begin\r
299 if(W_A == 16'h4007)begin\r
300 if(W_BDI == 8'h00) \r
301 on_game[0] <= 1;\r
302 else\r
303 on_game[0] <= 0;\r
304 end\r
305 if(W_A == 16'h4005)begin\r
306 if(W_BDI == 8'h03 || W_BDI == 8'h04 ) \r
307 on_game[1] <= 1;\r
308 else\r
309 on_game[1] <= 0;\r
310 end\r
311 end \r
312end\r
313\r
314`ifdef PSPAD_USE\r
315reg died;\r
316always @(posedge W_CPU_CLK)\r
317begin\r
318 if(~ZMWR)begin\r
319 if(W_A == 16'h4206)begin\r
320 if(W_BDI == 8'h00) \r
321 died <= 0;\r
322 else\r
323 died <= 1;\r
324 end\r
325 end\r
326end\r
327//---- PS_PAD Interface -----------------------------\r
328wire [8:0]ps_PSW;\r
329wire VIB_SW = died & (&on_game[1:0]);\r
330\r
331fpga_arcade_if pspad(\r
332\r
c3bcc38a 333.CLK_18M432(W_CLK_18M),\r
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334.I_RSTn(W_RESETn),\r
335.psCLK(psCLK),\r
336.psSEL(psSEL),\r
337.psTXD(psTXD),\r
338.psRXD(psRXD),\r
339.ps_PSW(ps_PSW),\r
340.I_VIB_SW(VIB_SW)\r
341\r
342);\r
343`endif\r
344//---- SW Interface ---------------------------------\r
345`ifdef PSPAD_USE\r
346wire L1 = I_PSW[2] & ps_PSW[2];\r
347wire R1 = I_PSW[3] & ps_PSW[3];\r
348wire U1 = I_PSW[0];\r
349wire D1 = I_PSW[1];\r
350wire J1 = I_PSW[4] & ps_PSW[8];\r
351\r
352wire S1 = (U1|J1) & ps_PSW[6];\r
353wire S2 = (D1|J1) & ps_PSW[7];\r
354\r
355wire C1 = (L1|R1|U1|~D1) & ps_PSW[4];\r
356`else\r
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357wire L1 = ! I_PSW[2];\r
358wire R1 = ! I_PSW[3];\r
359wire U1 = ! I_PSW[0];\r
360wire D1 = ! I_PSW[1];\r
361wire J1 = ! I_PSW[4];\r
782690d0 362\r
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363wire S1 = ! I_PSW[5];\r
364wire S2 = ! I_PSW[7];\r
782690d0 365\r
3fc34adf 366wire C1 = ! I_PSW[6];\r
782690d0 367`endif\r
3fc34adf 368wire C2 = ! I_PSW[8];\r
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369\r
370wire L2 = L1;\r
371wire R2 = R1;\r
372wire U2 = U1;\r
373wire D2 = D1;\r
374wire J2 = J1;\r
375\r
376mc_inport MC_INPORT(\r
377\r
378.I_COIN1(~C1), // ACTIVE HI\r
379.I_COIN2(~C2), // ACTIVE HI\r
380.I_1P_LE(~L1), // ACTIVE HI\r
381.I_1P_RI(~R1), // ACTIVE HI\r
382.I_1P_SH(~J1), // ACTIVE HI\r
383.I_2P_LE(~L2), // ACTIVE HI\r
384.I_2P_RI(~R2), // ACTIVE HI\r
385.I_2P_SH(~J2), // ACTIVE HI\r
386.I_1P_START(~S1), // ACTIVE HI\r
387.I_2P_START(~S2), // ACTIVE HI\r
388\r
389.I_SW0_OEn(W_SW0_OEn),\r
390.I_SW1_OEn(W_SW1_OEn),\r
391.I_DIP_OEn(W_DIP_OEn),\r
392\r
393.O_D(W_SW_DO)\r
394\r
395);\r
396\r
397//-----------------------------------------------------------------------------\r
398//------- ROM -------------------------------------------------------\r
399reg [18:0]ROM_A;\r
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400\r
401wire [18:0]W_WAV_A0,W_WAV_A1,W_WAV_A2;\r
402reg [7:0]W_WAV_D0,W_WAV_D1,W_WAV_D2;\r
403\r
36a47d3c 404wire [7:0]ROM_D;\r
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405\r
406galaxian_roms ROMS(\r
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407.I_ROM_CLK(W_CLK_12M),\r
408.I_ADDR({3'h0,W_A[15:0]}),\r
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409.O_DATA(ROM_D)\r
410);\r
411\r
36a47d3c 412always@(posedge W_CLK_12M)\r
782690d0 413begin\r
36a47d3c 414 W_CPU_ROM_DO <= ROM_D;\r
782690d0 415end\r
36a47d3c 416\r
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417//-----------------------------------------------------------------------------\r
418\r
419wire W_V_BL2n;\r
420\r
421mc_hv_count MC_HV(\r
422\r
423.I_CLK(WB_CLK_6M),\r
424.I_RSTn(W_RESETn),\r
425\r
426.O_H_CNT(W_H_CNT),\r
427.O_H_SYNC(W_H_SYNC),\r
428.O_H_BL(W_H_BL),\r
429.O_V_CNT(W_V_CNT),\r
430.O_V_SYNC(W_V_SYNC),\r
431.O_V_BL2n(W_V_BL2n),\r
432.O_V_BLn(W_V_BLn),\r
433.O_C_BLn(W_C_BLn)\r
434\r
435);\r
436\r
437//------ VIDEO -----------------------------\r
438wire W_8HF;\r
439wire W_1VF;\r
440wire W_C_BLnX;\r
441wire W_256HnX;\r
442wire W_MISSILEn;\r
443wire W_SHELLn;\r
444wire [1:0]W_VID;\r
445wire [2:0]W_COL;\r
446\r
447mc_video MC_VID(\r
c3bcc38a 448.I_CLK_18M(W_CLK_18M),\r
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449.I_CLK_12M(W_CLK_12M),\r
450.I_CLK_6M(W_CLK_6M),\r
4b3ff7d8 451.I_CLK_6Mn(W_CLK_6Mn),\r
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452.I_H_CNT(W_H_CNT),\r
453.I_V_CNT(W_V_CNT),\r
454.I_H_FLIP(W_H_FLIP),\r
455.I_V_FLIP(W_V_FLIP),\r
456.I_V_BLn(W_V_BLn),\r
457.I_C_BLn(W_C_BLn),\r
458\r
459.I_A(W_A[9:0]),\r
460.I_OBJ_SUB_A(3'b000),\r
461.I_BD(W_BDI),\r
462.I_OBJ_RAM_RQn(W_OBJ_RAM_RQn),\r
463.I_OBJ_RAM_RDn(W_OBJ_RAM_RDn),\r
464.I_OBJ_RAM_WRn(W_OBJ_RAM_WRn),\r
465.I_VID_RAM_RDn(W_VID_RAM_RDn),\r
466.I_VID_RAM_WRn(W_VID_RAM_WRn),\r
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467\r
468.O_C_BLnX(W_C_BLnX),\r
469.O_8HF(W_8HF),\r
470.O_256HnX(W_256HnX),\r
471.O_1VF(W_1VF),\r
472.O_MISSILEn(W_MISSILEn),\r
473.O_SHELLn(W_SHELLn),\r
474.O_BD(W_VID_DO),\r
475.O_VID(W_VID),\r
476.O_COL(W_COL)\r
477\r
478);\r
479\r
480wire W_C_BLX;\r
481wire W_STARS_OFFn;\r
482wire [2:0]W_VIDEO_R;\r
483wire [2:0]W_VIDEO_G;\r
484wire [1:0]W_VIDEO_B;\r
485\r
486mc_col_pal MC_COL_PAL(\r
487\r
488.I_CLK_12M(W_CLK_12M),\r
489.I_CLK_6M(W_CLK_6M),\r
490.I_VID(W_VID),\r
491.I_COL(W_COL),\r
492.I_C_BLnX(W_C_BLnX),\r
493\r
494.O_C_BLX(W_C_BLX),\r
495.O_STARS_OFFn(W_STARS_OFFn),\r
496.O_R(W_VIDEO_R),\r
497.O_G(W_VIDEO_G),\r
498.O_B(W_VIDEO_B)\r
499\r
500);\r
501\r
502wire [2:0]W_STARS_R;\r
503wire [2:0]W_STARS_G;\r
504wire [1:0]W_STARS_B;\r
505\r
506mc_stars MC_STARS( \r
507\r
c3bcc38a 508.I_CLK_18M(W_CLK_18M),\r
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509`ifdef DEVICE_CYCLONE\r
510.I_CLK_6M(~WB_CLK_6M),\r
511`endif\r
512`ifdef DEVICE_SPARTAN2E \r
513.I_CLK_6M(WB_CLK_6M), \r
514`endif\r
515.I_H_FLIP(W_H_FLIP),\r
516.I_V_SYNC(W_V_SYNC),\r
517.I_8HF(W_8HF),\r
518.I_256HnX(W_256HnX),\r
519.I_1VF(W_1VF),\r
520.I_2V(W_V_CNT[1]),\r
521.I_STARS_ON(W_STARS_ON),\r
522.I_STARS_OFFn(W_STARS_OFFn),\r
523\r
524.O_R(W_STARS_R),\r
525.O_G(W_STARS_G),\r
526.O_B(W_STARS_B),\r
527.O_NOISE()\r
528\r
529);\r
530\r
531wire [2:0]W_R;\r
532wire [2:0]W_G;\r
533wire [1:0]W_B;\r
534\r
535mc_vedio_mix MIX(\r
536\r
537.I_VID_R(W_VIDEO_R),\r
538.I_VID_G(W_VIDEO_G),\r
539.I_VID_B(W_VIDEO_B),\r
540.I_STR_R(W_STARS_R),\r
541.I_STR_G(W_STARS_G),\r
542.I_STR_B(W_STARS_B),\r
543\r
544.I_C_BLnXX(~W_C_BLX),\r
545.I_C_BLX(W_C_BLX | ~W_V_BL2n),\r
546.I_MISSILEn(W_MISSILEn),\r
547.I_SHELLn(W_SHELLn),\r
548\r
549.O_R(W_R),\r
550.O_G(W_G),\r
551.O_B(W_B)\r
552\r
553);\r
554\r
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555wire [2:0]W_VGA_R;\r
556wire [2:0]W_VGA_G;\r
557wire [1:0]W_VGA_B;\r
558\r
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559`ifdef VGA_USE\r
560mc_vga_if VGA(\r
561\r
562// input\r
563.I_CLK_1(W_CLK_6M),\r
564.I_CLK_2(W_CLK_12M),\r
565.I_R(W_R),\r
566.I_G(W_G),\r
567.I_B(W_B),\r
568.I_H_SYNC(W_H_SYNC),\r
569.I_V_SYNC(W_V_SYNC),\r
570// output\r
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571.O_R(W_VGA_R),\r
572.O_G(W_VGA_G),\r
573.O_B(W_VGA_B),\r
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574.O_H_SYNCn(O_VGA_H_SYNCn),\r
575.O_V_SYNCn(O_VGA_V_SYNCn)\r
576\r
577);\r
578\r
579`else\r
580\r
491f582f 581assign W_VGA_R[2:0] = W_R;\r
782690d0 582\r
491f582f 583assign W_VGA_G[2:0] = W_G;\r
782690d0 584\r
491f582f 585assign W_VGA_B[1:0] = W_B;\r
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586\r
587//assign O_VGA_H_SYNCn = W_H_SYNC | W_V_SYNC ; // AKIDUKI LCD USED\r
588assign O_VGA_H_SYNCn = ~W_H_SYNC ;\r
589assign O_VGA_V_SYNCn = ~W_V_SYNC ;\r
590\r
591`endif\r
592\r
e780c439 593assign O_VGA_R[3:0] = {W_VGA_R[0], W_VGA_R[1], W_VGA_R[2], 1'b0};\r
491f582f 594\r
e780c439 595assign O_VGA_G[3:0] = {W_VGA_G[0], W_VGA_G[1], W_VGA_G[2], 1'b0};\r
491f582f 596\r
e780c439 597assign O_VGA_B[3:0] = {W_VGA_B[0], W_VGA_B[1], 2'b0};\r
491f582f 598\r
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599wire [7:0]W_SDAT_A;\r
600\r
601mc_sound_a MC_SOUND_A(\r
602\r
603.I_CLK_12M(W_CLK_12M),\r
604.I_CLK_6M(W_CLK_6M),\r
605.I_H_CNT1(W_H_CNT[1]),\r
606.I_BD(W_BDI),\r
607.I_PITCHn(W_PITCHn),\r
608.I_VOL1(W_VOL1),\r
609.I_VOL2(W_VOL2),\r
610\r
611.O_SDAT(W_SDAT_A),\r
612.O_DO()\r
613\r
614);\r
615\r
616wire [7:0]W_SDAT_B;\r
617\r
618mc_sound_b MC_SOUND_B(\r
619\r
c3bcc38a 620.I_CLK1(W_CLK_18M),\r
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621.I_CLK2(W_CLK_6M),\r
622.I_RSTn(rst_count[3]),\r
623.I_SW({&on_game[1:0],W_HIT,W_FIRE}),\r
624\r
625.O_WAV_A0(W_WAV_A0),\r
626.O_WAV_A1(W_WAV_A1),\r
627.O_WAV_A2(W_WAV_A2),\r
628.I_WAV_D0(W_WAV_D0),\r
629.I_WAV_D1(W_WAV_D1),\r
630.I_WAV_D2(W_WAV_D2),\r
631\r
632.O_SDAT(W_SDAT_B)\r
633\r
634);\r
635\r
636wire W_DAC_A;\r
637wire W_DAC_B;\r
638\r
639assign O_SOUND_OUT_L = W_DAC_A;\r
640assign O_SOUND_OUT_R = W_DAC_B;\r
641\r
642dac wav_dac_a(\r
643\r
c3bcc38a 644.Clk(W_CLK_18M), \r
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645.Reset(~W_RESETn),\r
646.DACin(W_SDAT_A),\r
647.DACout(W_DAC_A)\r
648\r
649);\r
650\r
651dac wav_dac_b(\r
652\r
c3bcc38a 653.Clk(W_CLK_18M), \r
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654.Reset(~W_RESETn),\r
655.DACin(W_SDAT_B),\r
656.DACout(W_DAC_B)\r
657\r
658);\r
659\r
660\r
661endmodule\r
662\r
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