fix object position
[fpga-games] / galaxian / src / mc_video.v
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CommitLineData
1//===============================================================================\r
2// FPGA GALAXIAN VIDEO\r
3//\r
4// Version : 2.50\r
5//\r
6// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
7//\r
8// Important !\r
9//\r
10// This program is freeware for non-commercial use. \r
11// An author does no guarantee about this program.\r
12// You can use this under your own risk.\r
13//\r
14// 2004- 4-30 galaxian modify by K.DEGAWA\r
15// 2004- 5- 6 first release.\r
16// 2004- 8-23 Improvement with T80-IP.\r
17// 2004- 9-22 The problem which missile didn't sometimes come out from was improved.\r
18//================================================================================\r
19//-----------------------------------------------------------------------------------------\r
20// H_CNT[0],H_CNT[1],H_CNT[2],H_CNT[3],H_CNT[4],H_CNT[5],H_CNT[6],H_CNT[7],H_CNT[8], \r
21// 1 H 2 H 4H 8H 16 H 32H 64 H 128 H 256 H\r
22//-----------------------------------------------------------------------------------------\r
23// V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7] \r
24// 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V \r
25//-----------------------------------------------------------------------------------------\r
26\r
27module mc_video(\r
28\r
29I_CLK_18M,\r
30I_CLK_12M,\r
31I_CLK_6M,\r
32I_H_CNT,\r
33I_V_CNT,\r
34I_H_FLIP,\r
35I_V_FLIP,\r
36I_V_BLn,\r
37I_C_BLn,\r
38\r
39I_A,\r
40I_OBJ_SUB_A,\r
41I_BD,\r
42I_OBJ_RAM_RQn,\r
43I_OBJ_RAM_RDn,\r
44I_OBJ_RAM_WRn,\r
45I_VID_RAM_RDn,\r
46I_VID_RAM_WRn,\r
47\r
48O_C_BLnX,\r
49O_8HF,\r
50O_256HnX,\r
51O_1VF,\r
52O_MISSILEn,\r
53O_SHELLn,\r
54O_BD,\r
55O_VID,\r
56O_COL\r
57\r
58);\r
59\r
60input I_CLK_18M;\r
61input I_CLK_12M;\r
62input I_CLK_6M;\r
63input [8:0]I_H_CNT;\r
64input [7:0]I_V_CNT;\r
65input I_H_FLIP;\r
66input I_V_FLIP;\r
67input I_V_BLn;\r
68input I_C_BLn;\r
69\r
70input [9:0]I_A;\r
71input [7:0]I_BD;\r
72input [2:0]I_OBJ_SUB_A;\r
73input I_OBJ_RAM_RQn;\r
74input I_OBJ_RAM_RDn;\r
75input I_OBJ_RAM_WRn;\r
76input I_VID_RAM_RDn;\r
77input I_VID_RAM_WRn;\r
78\r
79output O_C_BLnX;\r
80output O_8HF;\r
81output O_256HnX;\r
82output O_1VF;\r
83output O_MISSILEn;\r
84output O_SHELLn;\r
85\r
86output [7:0]O_BD;\r
87output [1:0]O_VID;\r
88output [2:0]O_COL;\r
89\r
90wire WB_LDn;\r
91wire WB_CNTRLDn;\r
92wire WB_CNTRCLRn;\r
93wire WB_COLLn;\r
94wire WB_VPLn;\r
95wire WB_OBJDATALn;\r
96wire WB_MLDn;\r
97wire WB_SLDn;\r
98wire W_3D;\r
99reg W_LDn;\r
100reg W_CNTRLDn;\r
101reg W_CNTRCLRn;\r
102reg W_COLLn;\r
103reg W_VPLn;\r
104reg W_OBJDATALn;\r
105reg W_MLDn;\r
106reg W_SLDn;\r
107\r
108always@(negedge I_CLK_12M)\r
109begin\r
110 W_LDn <= WB_LDn;\r
111 W_CNTRLDn <= WB_CNTRLDn;\r
112 W_CNTRCLRn <= WB_CNTRCLRn;\r
113 W_COLLn <= WB_COLLn;\r
114 W_VPLn <= WB_VPLn;\r
115 W_OBJDATALn <= WB_OBJDATALn;\r
116 W_MLDn <= WB_MLDn;\r
117 W_SLDn <= WB_SLDn;\r
118end\r
119\r
120mc_ld_pls LD_PLS(\r
121\r
122.I_CLK_6M(I_CLK_6M),\r
123.I_H_CNT(I_H_CNT),\r
124.I_3D_DI(W_3D),\r
125\r
126.O_LDn(WB_LDn),\r
127.O_CNTRLDn(WB_CNTRLDn),\r
128.O_CNTRCLRn(WB_CNTRCLRn),\r
129.O_COLLn(WB_COLLn),\r
130.O_VPLn(WB_VPLn),\r
131.O_OBJDATALn(WB_OBJDATALn),\r
132.O_MLDn(WB_MLDn),\r
133.O_SLDn(WB_SLDn)\r
134\r
135);\r
136\r
137wire W_H_FLIP1 = ~I_H_CNT[8]&I_H_FLIP;\r
138\r
139wire [7:3]W_HF_CNT = I_H_CNT[7:3]^{5{W_H_FLIP1}};\r
140wire [7:0]W_VF_CNT = I_V_CNT[7:0]^{8{I_V_FLIP}};\r
141\r
142assign O_8HF = W_HF_CNT[3];\r
143assign O_1VF = W_VF_CNT[0];\r
144\r
145reg [7:0]W_OBJ_D;\r
146wire [3:0]W_6J_DA = {I_H_FLIP , W_HF_CNT[7],W_HF_CNT[3],I_H_CNT[2]};\r
147wire [3:0]W_6J_DB = {W_OBJ_D[6],W_HF_CNT[3]&I_H_CNT[1], I_H_CNT[2],I_H_CNT[1]};\r
148wire [3:0]W_6J_Q = I_H_CNT[8] ? W_6J_DB:W_6J_DA;\r
149\r
150wire W_H_FLIP2 = W_6J_Q[3];\r
151// Prats 4F,5F\r
152wire [7:0]W_OBJ_RAM_AB = {1'b0,I_H_CNT[8],W_6J_Q[2],W_HF_CNT[6:4],W_6J_Q[1:0]};\r
153wire [7:0]W_OBJ_RAM_A = I_OBJ_RAM_RQn ? W_OBJ_RAM_AB: I_A[7:0] ;\r
154\r
155wire [7:0]W_OBJ_RAM_DOA,W_OBJ_RAM_DOB;\r
156\r
157reg [7:0]W_H_POSI;\r
158always@(posedge I_CLK_6M) W_H_POSI <= W_OBJ_RAM_DOB;\r
159\r
160mc_obj_ram OBJ_RAM(\r
161\r
162.I_CLKA(I_CLK_12M),\r
163.I_ADDRA(I_A[7:0]),\r
164.I_WEA(~I_OBJ_RAM_WRn),\r
165.I_CEA(~I_OBJ_RAM_RQn),\r
166.I_DA(I_BD),\r
167.O_DA(W_OBJ_RAM_DOA),\r
168\r
169.I_CLKB(I_CLK_12M),\r
170.I_ADDRB(W_OBJ_RAM_AB),\r
171.I_WEB(1'b0),\r
172.I_CEB(1'b1),\r
173.I_DB(8'h00),\r
174.O_DB(W_OBJ_RAM_DOB)\r
175\r
176);\r
177\r
178wire [7:0]W_OBJ_RAM_D = I_OBJ_RAM_RDn ? 8'h00: W_OBJ_RAM_DOA;\r
179// Prats 4L\r
180always@(posedge W_OBJDATALn) W_OBJ_D <= W_H_POSI; \r
181// Prats 4,5N\r
182\r
183wire [8:0]W_45N_Q = W_VF_CNT[7:0] + W_H_POSI ;\r
184assign W_3D = ~(&W_45N_Q[7:0]); \r
185\r
186reg [7:0]W_2M_Q;\r
187always@(posedge W_VPLn or negedge I_V_BLn)\r
188begin\r
189 if(I_V_BLn==1'b0)\r
190 W_2M_Q <= 0;\r
191 else\r
192 W_2M_Q <= W_45N_Q[7:0];\r
193end\r
194\r
195wire W_2N = I_H_CNT[8]&W_OBJ_D[7];\r
196wire [3:0]W_1M = W_2M_Q[3:0]^{W_2N,W_2N,W_2N,W_2N};\r
197\r
198wire W_VID_RAM_CSn = I_VID_RAM_RDn & I_VID_RAM_WRn;\r
199\r
200wire [7:0]W_VID_RAM_DI = I_VID_RAM_WRn ? 8'h00 : I_BD ;\r
201wire [7:0]W_VID_RAM_DOA;\r
202\r
203wire [11:0]W_VID_RAM_AA = {~(&W_2M_Q[7:4]),W_VID_RAM_CSn, 10'h00 /*I_A[9:0]*/};\r
204wire [11:0]W_VID_RAM_AB = { 1'b0, 1'b0,W_2M_Q[7:4],W_1M[3],W_HF_CNT[7:3]};\r
205\r
206wire [11:0]W_VID_RAM_A = I_C_BLn ? W_VID_RAM_AB:W_VID_RAM_AA;\r
207\r
208wire [7:0]W_VID_RAM_D = I_VID_RAM_RDn ? 8'h00 :W_VID_RAM_DOA;\r
209\r
210wire [7:0]W_VID_RAM_DOB;\r
211\r
212mc_vid_ram VID_RAM(\r
213\r
214.I_CLKA(I_CLK_12M),\r
215.I_ADDRA(I_A[9:0]),\r
216.I_DA(W_VID_RAM_DI),\r
217.I_WEA(~I_VID_RAM_WRn),\r
218.I_CEA(~W_VID_RAM_CSn),\r
219.O_DA(W_VID_RAM_DOA),\r
220\r
221.I_CLKB(I_CLK_12M),\r
222.I_ADDRB(W_VID_RAM_A[9:0]),\r
223.I_DB(8'h00),\r
224.I_WEB(1'b0),\r
225.I_CEB(1'b1),\r
226.O_DB(W_VID_RAM_DOB)\r
227\r
228);\r
229//-- VIDEO DATA OUTPUT --------------\r
230assign O_BD = W_OBJ_RAM_D | W_VID_RAM_D;\r
231\r
232wire W_SRLD = ~(W_LDn | W_VID_RAM_A[11]);\r
233\r
234wire [7:0]W_OBJ_ROM_AB = {W_OBJ_D[5:0],W_1M[3],W_OBJ_D[6]^I_H_CNT[3]};\r
235\r
236wire [7:0]W_OBJ_ROM_A = I_H_CNT[8] ? W_OBJ_ROM_AB: W_VID_RAM_DOB;\r
237\r
238wire [10:0]W_O_OBJ_ROM_A = {W_OBJ_ROM_A,W_1M[2:0]};\r
239\r
240wire [7:0]W_1K_D;\r
241wire [7:0]W_1H_D;\r
242\r
243//1K VID-Rom\r
244GALAXIAN_1K K_ROM(\r
245.CLK(I_CLK_12M),\r
246.ADDR(W_O_OBJ_ROM_A),\r
247.DATA(W_1K_D),\r
248.ENA(1'b1)\r
249);\r
250\r
251//1H VID-Rom\r
252GALAXIAN_1H H_ROM(\r
253.CLK(I_CLK_12M),\r
254.ADDR(W_O_OBJ_ROM_A),\r
255.DATA(W_1H_D),\r
256.ENA(1'b1)\r
257);\r
258\r
259\r
260//---------------------------------------------------------------------------------\r
261wire W_2L_Qa,W_2K_Qd;\r
262wire W_2J_Qa,W_2H_Qd;\r
263wire W_H_FLIP2X;\r
264\r
265wire [3:0]W_3L_A = {W_2J_Qa,W_2L_Qa, 1'b1,W_SRLD};\r
266wire [3:0]W_3L_B = {W_2H_Qd,W_2K_Qd,W_SRLD, 1'b1}; \r
267wire [3:0]W_3L_Y = W_H_FLIP2X ? W_3L_B: W_3L_A; // [3]=RAW1,[2]=RAW0\r
268\r
269wire W_RAW0 = W_3L_Y[2];\r
270wire W_RAW1 = W_3L_Y[3];\r
271\r
272wire W_SRCLK = I_CLK_6M;\r
273//------ PARTS 2KL ---------------------------------------------- \r
274wire [1:0]C_2KL = W_3L_Y[1:0];\r
275wire [7:0]I_2KL = W_1K_D;\r
276reg [7:0]reg_2KL;\r
277\r
278assign W_2L_Qa = reg_2KL[7];\r
279assign W_2K_Qd = reg_2KL[0];\r
280always@(posedge W_SRCLK)\r
281begin\r
282 case(C_2KL)\r
283 2'b00: reg_2KL <= reg_2KL;\r
284 2'b10: reg_2KL <= {reg_2KL[6:0],1'b0};\r
285 2'b01: reg_2KL <= {1'b0,reg_2KL[7:1]};\r
286 2'b11: reg_2KL <= I_2KL;\r
287 endcase\r
288end\r
289//------ PARTS 2HJ ---------------------------------------------- \r
290wire [1:0]C_2HJ = W_3L_Y[1:0];\r
291wire [7:0]I_2HJ = W_1H_D;\r
292reg [7:0]reg_2HJ;\r
293\r
294assign W_2J_Qa = reg_2HJ[7];\r
295assign W_2H_Qd = reg_2HJ[0];\r
296always@(posedge W_SRCLK)\r
297begin\r
298 case(C_2HJ)\r
299 2'b00: reg_2HJ <= reg_2HJ;\r
300 2'b10: reg_2HJ <= {reg_2HJ[6:0],1'b0};\r
301 2'b01: reg_2HJ <= {1'b0,reg_2HJ[7:1]};\r
302 2'b11: reg_2HJ <= I_2HJ;\r
303 endcase\r
304end\r
305\r
306//----- SHT2 -----------------------------------------------------\r
307// Prats 6K\r
308reg [2:0]W_6K_Q;\r
309always@(posedge W_COLLn) W_6K_Q <= W_H_POSI[2:0];\r
310\r
311// Prats 6P\r
312reg [6:0]W_6P_Q;\r
313always@(posedge I_CLK_6M)\r
314begin\r
315 if(W_LDn==1'b0) W_6P_Q <= {W_H_FLIP2,W_H_FLIP1,I_C_BLn,~I_H_CNT[8],W_6K_Q[2:0]};\r
316 else W_6P_Q <= W_6P_Q;\r
317end\r
318\r
319assign W_H_FLIP2X = W_6P_Q[6];\r
320wire W_H_FLIP1X = W_6P_Q[5];\r
321wire W_C_BLnX = W_6P_Q[4];\r
322wire W_256HnX = W_6P_Q[3];\r
323wire [2:0]W_CD = W_6P_Q[2:0];\r
324\r
325assign O_256HnX = W_256HnX;\r
326assign O_C_BLnX = W_C_BLnX;\r
327\r
328wire W_45T_CLR = W_CNTRCLRn | W_256HnX ;\r
329reg [7:0]W_45T_Q;\r
330\r
331always@(posedge I_CLK_6M)\r
332begin\r
333 if(W_45T_CLR==1'b0)\r
334 W_45T_Q <= 0;\r
335 else if(W_CNTRLDn==1'b0)\r
336 W_45T_Q <= W_H_POSI;\r
337 else\r
338 W_45T_Q <= W_45T_Q + 1;\r
339end\r
340\r
341wire [7:0]W_LRAM_A = W_45T_Q^{8{W_H_FLIP1X}};\r
342\r
343wire [4:0]W_LRAM_DI;\r
344wire [4:0]W_LRAM_DO;\r
345\r
346reg [1:0]W_RV;\r
347reg [2:0]W_RC;\r
348\r
349always@(negedge I_CLK_6M)\r
350begin\r
351 W_RV <= W_LRAM_DO[1:0]; \r
352 W_RC <= W_LRAM_DO[4:2];\r
353end\r
354\r
355wire W_LRAM_AND = ~(~((W_LRAM_A[4]|W_LRAM_A[5])|(W_LRAM_A[6]|W_LRAM_A[7]))|W_256HnX );\r
356wire W_RAW_OR = W_RAW0 | W_RAW1 ;\r
357\r
358wire [1:0]W_VID;\r
359wire [2:0]W_COL;\r
360\r
361assign W_VID[0] = ~(~(W_RAW0&W_RV[1])&W_RV[0]);\r
362assign W_VID[1] = ~(~(W_RAW1&W_RV[0])&W_RV[1]);\r
363assign W_COL[0] = ~(~(W_RAW_OR&W_CD[0]&W_RC[1]&W_RC[2])&W_RC[0]);\r
364assign W_COL[1] = ~(~(W_RAW_OR&W_CD[1]&W_RC[2]&W_RC[0])&W_RC[1]);\r
365assign W_COL[2] = ~(~(W_RAW_OR&W_CD[2]&W_RC[0]&W_RC[1])&W_RC[2]);\r
366\r
367assign O_VID = W_VID;\r
368assign O_COL = W_COL;\r
369\r
370assign W_LRAM_DI[0] = W_LRAM_AND&W_VID[0];\r
371assign W_LRAM_DI[1] = W_LRAM_AND&W_VID[1]; \r
372assign W_LRAM_DI[2] = W_LRAM_AND&W_COL[0];\r
373assign W_LRAM_DI[3] = W_LRAM_AND&W_COL[1];\r
374assign W_LRAM_DI[4] = W_LRAM_AND&W_COL[2];\r
375\r
376mc_lram LRAM(\r
377\r
378.I_CLK(I_CLK_18M),\r
379.I_ADDR(W_LRAM_A),\r
380.I_WE(I_CLK_6M),\r
381.I_D(W_LRAM_DI),\r
382.O_Dn(W_LRAM_DO)\r
383\r
384);\r
385\r
386mc_missile MISSILE(\r
387\r
388.I_CLK_18M(I_CLK_18M),\r
389.I_CLK_6M(I_CLK_6M),\r
390.I_C_BLn_X(W_C_BLnX),\r
391.I_MLDn(W_MLDn),\r
392.I_SLDn(W_SLDn),\r
393.I_HPOS(W_H_POSI),\r
394\r
395.O_MISSILEn(O_MISSILEn),\r
396.O_SHELLn(O_SHELLn)\r
397\r
398);\r
399\r
400endmodule\r
401\r
402\r
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