git.zerfleddert.de Git - fpga-games/blame_incremental - galaxian/src/mc_video.v

//===============================================================================\r
// FPGA GALAXIAN  VIDEO\r
//\r
// Version : 2.50\r
//\r
// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
//\r
// Important !\r
//\r
// This program is freeware for non-commercial use. \r
// An author does no guarantee about this program.\r
// You can use this under your own risk.\r
//\r
// 2004- 4-30  galaxian modify by K.DEGAWA\r
// 2004- 5- 6  first release.\r
// 2004- 8-23  Improvement with T80-IP.\r
// 2004- 9-22  The problem which missile didn't sometimes come out from was improved.\r
//================================================================================\r
//-----------------------------------------------------------------------------------------\r
// H_CNT[0],H_CNT[1],H_CNT[2],H_CNT[3],H_CNT[4],H_CNT[5],H_CNT[6],H_CNT[7],H_CNT[8],  \r
//    1 H     2 H      4H       8H       16 H     32H      64 H     128 H   256 H\r
//-----------------------------------------------------------------------------------------\r
// V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7]  \r
//    1 V      2 V       4 V       8 V       16 V      32 V      64 V     128 V \r
//-----------------------------------------------------------------------------------------\r
\r
module mc_video(\r
\r
I_CLK_18M,\r
I_CLK_12M,\r
I_CLK_6M,\r
I_H_CNT,\r
I_V_CNT,\r
I_H_FLIP,\r
I_V_FLIP,\r
I_V_BLn,\r
I_C_BLn,\r
\r
I_A,\r
I_OBJ_SUB_A,\r
I_BD,\r
I_OBJ_RAM_RQn,\r
I_OBJ_RAM_RDn,\r
I_OBJ_RAM_WRn,\r
I_VID_RAM_RDn,\r
I_VID_RAM_WRn,\r
\r
O_OBJ_ROM_A,\r
I_OBJ_ROM_A_D,\r
I_OBJ_ROM_B_D,\r
\r
O_C_BLnX,\r
O_8HF,\r
O_256HnX,\r
O_1VF,\r
O_MISSILEn,\r
O_SHELLn,\r
O_BD,\r
O_VID,\r
O_COL\r
\r
);\r
\r
input  I_CLK_18M;\r
input  I_CLK_12M;\r
input  I_CLK_6M;\r
input  [8:0]I_H_CNT;\r
input  [7:0]I_V_CNT;\r
input  I_H_FLIP;\r
input  I_V_FLIP;\r
input  I_V_BLn;\r
input  I_C_BLn;\r
\r
input  [9:0]I_A;\r
input  [7:0]I_BD;\r
input  [2:0]I_OBJ_SUB_A;\r
input  I_OBJ_RAM_RQn;\r
input  I_OBJ_RAM_RDn;\r
input  I_OBJ_RAM_WRn;\r
input  I_VID_RAM_RDn;\r
input  I_VID_RAM_WRn;\r
\r
output [10:0]O_OBJ_ROM_A;\r
input  [7:0]I_OBJ_ROM_A_D;\r
input  [7:0]I_OBJ_ROM_B_D;\r
\r
output O_C_BLnX;\r
output O_8HF;\r
output O_256HnX;\r
output O_1VF;\r
output O_MISSILEn;\r
output O_SHELLn;\r
\r
output [7:0]O_BD;\r
output [1:0]O_VID;\r
output [2:0]O_COL;\r
\r
wire   WB_LDn;\r
wire   WB_CNTRLDn;\r
wire   WB_CNTRCLRn;\r
wire   WB_COLLn;\r
wire   WB_VPLn;\r
wire   WB_OBJDATALn;\r
wire   WB_MLDn;\r
wire   WB_SLDn;\r
wire   W_3D;\r
reg    W_LDn;\r
reg    W_CNTRLDn;\r
reg    W_CNTRCLRn;\r
reg    W_COLLn;\r
reg    W_VPLn;\r
reg    W_OBJDATALn;\r
reg    W_MLDn;\r
reg    W_SLDn;\r
\r
always@(negedge I_CLK_12M)\r
begin\r
   W_LDn <= WB_LDn;\r
   W_CNTRLDn <= WB_CNTRLDn;\r
   W_CNTRCLRn <= WB_CNTRCLRn;\r
   W_COLLn <= WB_COLLn;\r
   W_VPLn <= WB_VPLn;\r
   W_OBJDATALn <= WB_OBJDATALn;\r
   W_MLDn <= WB_MLDn;\r
   W_SLDn <= WB_SLDn;\r
end\r
\r
mc_ld_pls LD_PLS(\r
\r
.I_CLK_6M(~I_CLK_6M),\r
.I_H_CNT(I_H_CNT),\r
.I_3D_DI(W_3D),\r
\r
.O_LDn(WB_LDn),\r
.O_CNTRLDn(WB_CNTRLDn),\r
.O_CNTRCLRn(WB_CNTRCLRn),\r
.O_COLLn(WB_COLLn),\r
.O_VPLn(WB_VPLn),\r
.O_OBJDATALn(WB_OBJDATALn),\r
.O_MLDn(WB_MLDn),\r
.O_SLDn(WB_SLDn)\r
\r
);\r
\r
wire   W_H_FLIP1 = ~I_H_CNT[8]&I_H_FLIP;\r
\r
wire   [7:3]W_HF_CNT = I_H_CNT[7:3]^{5{W_H_FLIP1}};\r
wire   [7:0]W_VF_CNT = I_V_CNT[7:0]^{8{I_V_FLIP}};\r
\r
assign O_8HF = W_HF_CNT[3];\r
assign O_1VF = W_VF_CNT[0];\r
\r
reg    [7:0]W_OBJ_D;\r
wire   [3:0]W_6J_DA = {I_H_FLIP  ,           W_HF_CNT[7],W_HF_CNT[3],I_H_CNT[2]};\r
wire   [3:0]W_6J_DB = {W_OBJ_D[6],W_HF_CNT[3]&I_H_CNT[1], I_H_CNT[2],I_H_CNT[1]};\r
wire   [3:0]W_6J_Q  = I_H_CNT[8] ? W_6J_DB:W_6J_DA;\r
\r
wire   W_H_FLIP2 = W_6J_Q[3];\r
//   Prats  4F,5F\r
wire   [7:0]W_OBJ_RAM_AB = {1'b0,I_H_CNT[8],W_6J_Q[2],W_HF_CNT[6:4],W_6J_Q[1:0]};\r
wire   [7:0]W_OBJ_RAM_A  = I_OBJ_RAM_RQn ? W_OBJ_RAM_AB: I_A[7:0] ;\r
\r
wire   [7:0]W_OBJ_RAM_DOA,W_OBJ_RAM_DOB;\r
\r
reg    [7:0]W_H_POSI;\r
always@(posedge I_CLK_12M) W_H_POSI <= W_OBJ_RAM_DOB;\r
\r
mc_obj_ram OBJ_RAM(\r
\r
.I_CLKA(I_CLK_12M),\r
.I_ADDRA(I_A[7:0]),\r
.I_WEA(~I_OBJ_RAM_WRn),\r
.I_CEA(~I_OBJ_RAM_RQn),\r
.I_DA(I_BD),\r
.O_DA(W_OBJ_RAM_DOA),\r
\r
.I_CLKB(I_CLK_12M),\r
.I_ADDRB(W_OBJ_RAM_AB),\r
.I_WEB(1'b0),\r
.I_CEB(1'b1),\r
.I_DB(8'h00),\r
.O_DB(W_OBJ_RAM_DOB)\r
\r
);\r
\r
wire   [7:0]W_OBJ_RAM_D = I_OBJ_RAM_RDn ?  8'h00: W_OBJ_RAM_DOA;\r
//   Prats  4L\r
always@(posedge W_OBJDATALn) W_OBJ_D <= W_H_POSI; \r
//   Prats  4,5N\r
\r
wire   [8:0]W_45N_Q = W_VF_CNT[7:0] + W_H_POSI ;\r
assign W_3D = ~(&W_45N_Q[7:0]); \r
\r
reg    [7:0]W_2M_Q;\r
always@(posedge W_VPLn or negedge I_V_BLn)\r
begin\r
   if(I_V_BLn==1'b0)\r
      W_2M_Q <= 0;\r
   else\r
      W_2M_Q <= W_45N_Q[7:0];\r
end\r
\r
wire   W_2N = I_H_CNT[8]&W_OBJ_D[7];\r
wire   [3:0]W_1M = W_2M_Q[3:0]^{W_2N,W_2N,W_2N,W_2N};\r
\r
wire   W_VID_RAM_CSn = I_VID_RAM_RDn & I_VID_RAM_WRn;\r
\r
wire   [7:0]W_VID_RAM_DI = I_VID_RAM_WRn ? 8'h00 : I_BD ;\r
wire   [7:0]W_VID_RAM_DOA;\r
\r
wire   [11:0]W_VID_RAM_AA = {~(&W_2M_Q[7:4]),W_VID_RAM_CSn,              10'h00 /*I_A[9:0]*/};\r
wire   [11:0]W_VID_RAM_AB = {           1'b0,         1'b0,W_2M_Q[7:4],W_1M[3],W_HF_CNT[7:3]};\r
\r
wire   [11:0]W_VID_RAM_A  = I_C_BLn ? W_VID_RAM_AB:W_VID_RAM_AA;\r
\r
wire   [7:0]W_VID_RAM_D = I_VID_RAM_RDn ? 8'h00 :W_VID_RAM_DOA;\r
\r
wire   [7:0]W_VID_RAM_DOB;\r
\r
mc_vid_ram VID_RAM(\r
\r
.I_CLKA(I_CLK_12M),\r
.I_ADDRA(I_A[9:0]),\r
.I_DA(W_VID_RAM_DI),\r
.I_WEA(~I_VID_RAM_WRn),\r
.I_CEA(~W_VID_RAM_CSn),\r
.O_DA(W_VID_RAM_DOA),\r
\r
.I_CLKB(I_CLK_12M),\r
.I_ADDRB(W_VID_RAM_A[9:0]),\r
.I_DB(8'h00),\r
.I_WEB(1'b0),\r
.I_CEB(1'b1),\r
.O_DB(W_VID_RAM_DOB)\r
\r
);\r
//--  VIDEO DATA OUTPUT  --------------\r
assign O_BD = W_OBJ_RAM_D | W_VID_RAM_D;\r
\r
wire   W_SRLD = ~(W_LDn | W_VID_RAM_A[11]);\r
\r
wire   [7:0]W_OBJ_ROM_AB = {W_OBJ_D[5:0],W_1M[3],W_OBJ_D[6]^I_H_CNT[3]};\r
\r
wire   [7:0]W_OBJ_ROM_A = I_H_CNT[8] ? W_OBJ_ROM_AB: W_VID_RAM_DOB;\r
\r
assign O_OBJ_ROM_A = {W_OBJ_ROM_A,W_1M[2:0]};\r
\r
wire   [7:0]W_1K_D = I_OBJ_ROM_A_D;\r
wire   [7:0]W_1H_D = I_OBJ_ROM_B_D;\r
\r
//---------------------------------------------------------------------------------\r
wire   W_2L_Qa,W_2K_Qd;\r
wire   W_2J_Qa,W_2H_Qd;\r
wire   W_H_FLIP2X;\r
\r
wire   [3:0]W_3L_A = {W_2J_Qa,W_2L_Qa,  1'b1,W_SRLD};\r
wire   [3:0]W_3L_B = {W_2H_Qd,W_2K_Qd,W_SRLD,  1'b1};  \r
wire   [3:0]W_3L_Y = W_H_FLIP2X ? W_3L_B: W_3L_A;   //  [3]=RAW1,[2]=RAW0\r
\r
wire   W_RAW0 = W_3L_Y[2];\r
wire   W_RAW1 = W_3L_Y[3];\r
\r
wire   W_SRCLK = I_CLK_6M;\r
//------  PARTS 2KL  ---------------------------------------------- \r
wire   [1:0]C_2KL = W_3L_Y[1:0];\r
wire   [7:0]I_2KL = W_1K_D;\r
reg    [7:0]reg_2KL;\r
\r
assign W_2L_Qa = reg_2KL[7];\r
assign W_2K_Qd = reg_2KL[0];\r
always@(posedge W_SRCLK)\r
begin\r
   case(C_2KL)\r
      2'b00: reg_2KL <= reg_2KL;\r
      2'b10: reg_2KL <= {reg_2KL[6:0],1'b0};\r
      2'b01: reg_2KL <= {1'b0,reg_2KL[7:1]};\r
      2'b11: reg_2KL <= I_2KL;\r
   endcase\r
end\r
//------  PARTS 2HJ  ---------------------------------------------- \r
wire   [1:0]C_2HJ = W_3L_Y[1:0];\r
wire   [7:0]I_2HJ = W_1H_D;\r
reg    [7:0]reg_2HJ;\r
\r
assign W_2J_Qa = reg_2HJ[7];\r
assign W_2H_Qd = reg_2HJ[0];\r
always@(posedge W_SRCLK)\r
begin\r
   case(C_2HJ)\r
      2'b00: reg_2HJ <= reg_2HJ;\r
      2'b10: reg_2HJ <= {reg_2HJ[6:0],1'b0};\r
      2'b01: reg_2HJ <= {1'b0,reg_2HJ[7:1]};\r
      2'b11: reg_2HJ <= I_2HJ;\r
   endcase\r
end\r
\r
//-----  SHT2 -----------------------------------------------------\r
//  Prats 6K\r
reg    [2:0]W_6K_Q;\r
always@(posedge W_COLLn) W_6K_Q <= W_H_POSI[2:0];\r
\r
//  Prats 6P\r
reg    [6:0]W_6P_Q;\r
always@(posedge I_CLK_6M)\r
begin\r
   if(W_LDn==1'b0) W_6P_Q <= {W_H_FLIP2,W_H_FLIP1,I_C_BLn,~I_H_CNT[8],W_6K_Q[2:0]};\r
   else            W_6P_Q <= W_6P_Q;\r
end\r
\r
assign W_H_FLIP2X = W_6P_Q[6];\r
wire   W_H_FLIP1X = W_6P_Q[5];\r
wire   W_C_BLnX   = W_6P_Q[4];\r
wire   W_256HnX   = W_6P_Q[3];\r
wire   [2:0]W_CD  = W_6P_Q[2:0];\r
\r
assign O_256HnX   = W_256HnX;\r
assign O_C_BLnX   = W_C_BLnX;\r
\r
wire   W_45T_CLR = W_CNTRCLRn | W_256HnX ;\r
reg    [7:0]W_45T_Q;\r
\r
always@(posedge I_CLK_6M)\r
begin\r
   if(W_45T_CLR==1'b0)\r
      W_45T_Q <= 0;\r
   else if(W_CNTRLDn==1'b0)\r
      W_45T_Q <= W_H_POSI;\r
   else\r
      W_45T_Q <= W_45T_Q + 1;\r
end\r
\r
wire   [7:0]W_LRAM_A = W_45T_Q^{8{W_H_FLIP1X}};\r
wire   W_LRAM_WE = ~I_CLK_6M;\r
\r
wire   [4:0]W_LRAM_DI;\r
wire   [4:0]W_LRAM_DO;\r
\r
reg    [1:0]W_RV;\r
reg    [2:0]W_RC;\r
wire   W_1U_CLK = ~I_CLK_6M;\r
\r
always@(posedge W_1U_CLK)\r
begin\r
      W_RV <= W_LRAM_DO[1:0];    \r
      W_RC <= W_LRAM_DO[4:2];\r
end\r
\r
wire   W_LRAM_AND = ~(~((W_LRAM_A[4]|W_LRAM_A[5])|(W_LRAM_A[6]|W_LRAM_A[7]))|W_256HnX );\r
wire   W_RAW_OR = W_RAW0 | W_RAW1 ;\r
\r
wire   [1:0]W_VID;\r
wire   [2:0]W_COL;\r
\r
assign W_VID[0] = ~(~(W_RAW0&W_RV[1])&W_RV[0]);\r
assign W_VID[1] = ~(~(W_RAW1&W_RV[0])&W_RV[1]);\r
assign W_COL[0] = ~(~(W_RAW_OR&W_CD[0]&W_RC[1]&W_RC[2])&W_RC[0]);\r
assign W_COL[1] = ~(~(W_RAW_OR&W_CD[1]&W_RC[2]&W_RC[0])&W_RC[1]);\r
assign W_COL[2] = ~(~(W_RAW_OR&W_CD[2]&W_RC[0]&W_RC[1])&W_RC[2]);\r
\r
assign O_VID = W_VID;\r
assign O_COL = W_COL;\r
\r
assign W_LRAM_DI[0] = W_LRAM_AND&W_VID[0];\r
assign W_LRAM_DI[1] = W_LRAM_AND&W_VID[1]; \r
assign W_LRAM_DI[2] = W_LRAM_AND&W_COL[0];\r
assign W_LRAM_DI[3] = W_LRAM_AND&W_COL[1];\r
assign W_LRAM_DI[4] = W_LRAM_AND&W_COL[2];\r
\r
mc_lram LRAM(\r
\r
.I_CLK(I_CLK_18M),\r
.I_ADDR(W_LRAM_A),\r
.I_WE(W_LRAM_WE),\r
.I_D(W_LRAM_DI),\r
.O_Dn(W_LRAM_DO)\r
\r
);\r
\r
mc_missile MISSILE(\r
\r
.I_CLK_18M(I_CLK_18M),\r
.I_CLK_6M(I_CLK_6M),\r
.I_C_BLn_X(W_C_BLnX),\r
.I_MLDn(W_MLDn),\r
.I_SLDn(W_SLDn),\r
.I_HPOS(W_H_POSI),\r
\r
.O_MISSILEn(O_MISSILEn),\r
.O_SHELLn(O_SHELLn)\r
\r
);\r
\r
endmodule\r
\r
\r
Commit	Line	Data
	1	//===============================================================================\r
	2	// FPGA GALAXIAN VIDEO\r
	3	//\r
	4	// Version : 2.50\r
	5	//\r
	6	// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
	7	//\r
	8	// Important !\r
	9	//\r
	10	// This program is freeware for non-commercial use. \r
	11	// An author does no guarantee about this program.\r
	12	// You can use this under your own risk.\r
	13	//\r
	14	// 2004- 4-30 galaxian modify by K.DEGAWA\r
	15	// 2004- 5- 6 first release.\r
	16	// 2004- 8-23 Improvement with T80-IP.\r
	17	// 2004- 9-22 The problem which missile didn't sometimes come out from was improved.\r
	18	//================================================================================\r
	19	//-----------------------------------------------------------------------------------------\r
	20	// H_CNT[0],H_CNT[1],H_CNT[2],H_CNT[3],H_CNT[4],H_CNT[5],H_CNT[6],H_CNT[7],H_CNT[8], \r
	21	// 1 H 2 H 4H 8H 16 H 32H 64 H 128 H 256 H\r
	22	//-----------------------------------------------------------------------------------------\r
	23	// V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7] \r
	24	// 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V \r
	25	//-----------------------------------------------------------------------------------------\r
	26	\r
	27	module mc_video(\r
	28	\r
	29	I_CLK_18M,\r
	30	I_CLK_12M,\r
	31	I_CLK_6M,\r
	32	I_H_CNT,\r
	33	I_V_CNT,\r
	34	I_H_FLIP,\r
	35	I_V_FLIP,\r
	36	I_V_BLn,\r
	37	I_C_BLn,\r
	38	\r
	39	I_A,\r
	40	I_OBJ_SUB_A,\r
	41	I_BD,\r
	42	I_OBJ_RAM_RQn,\r
	43	I_OBJ_RAM_RDn,\r
	44	I_OBJ_RAM_WRn,\r
	45	I_VID_RAM_RDn,\r
	46	I_VID_RAM_WRn,\r
	47	\r
	48	O_OBJ_ROM_A,\r
	49	I_OBJ_ROM_A_D,\r
	50	I_OBJ_ROM_B_D,\r
	51	\r
	52	O_C_BLnX,\r
	53	O_8HF,\r
	54	O_256HnX,\r
	55	O_1VF,\r
	56	O_MISSILEn,\r
	57	O_SHELLn,\r
	58	O_BD,\r
	59	O_VID,\r
	60	O_COL\r
	61	\r
	62	);\r
	63	\r
	64	input I_CLK_18M;\r
	65	input I_CLK_12M;\r
	66	input I_CLK_6M;\r
	67	input [8:0]I_H_CNT;\r
	68	input [7:0]I_V_CNT;\r
	69	input I_H_FLIP;\r
	70	input I_V_FLIP;\r
	71	input I_V_BLn;\r
	72	input I_C_BLn;\r
	73	\r
	74	input [9:0]I_A;\r
	75	input [7:0]I_BD;\r
	76	input [2:0]I_OBJ_SUB_A;\r
	77	input I_OBJ_RAM_RQn;\r
	78	input I_OBJ_RAM_RDn;\r
	79	input I_OBJ_RAM_WRn;\r
	80	input I_VID_RAM_RDn;\r
	81	input I_VID_RAM_WRn;\r
	82	\r
	83	output [10:0]O_OBJ_ROM_A;\r
	84	input [7:0]I_OBJ_ROM_A_D;\r
	85	input [7:0]I_OBJ_ROM_B_D;\r
	86	\r
	87	output O_C_BLnX;\r
	88	output O_8HF;\r
	89	output O_256HnX;\r
	90	output O_1VF;\r
	91	output O_MISSILEn;\r
	92	output O_SHELLn;\r
	93	\r
	94	output [7:0]O_BD;\r
	95	output [1:0]O_VID;\r
	96	output [2:0]O_COL;\r
	97	\r
	98	wire WB_LDn;\r
	99	wire WB_CNTRLDn;\r
	100	wire WB_CNTRCLRn;\r
	101	wire WB_COLLn;\r
	102	wire WB_VPLn;\r
	103	wire WB_OBJDATALn;\r
	104	wire WB_MLDn;\r
	105	wire WB_SLDn;\r
	106	wire W_3D;\r
	107	reg W_LDn;\r
	108	reg W_CNTRLDn;\r
	109	reg W_CNTRCLRn;\r
	110	reg W_COLLn;\r
	111	reg W_VPLn;\r
	112	reg W_OBJDATALn;\r
	113	reg W_MLDn;\r
	114	reg W_SLDn;\r
	115	\r
	116	always@(negedge I_CLK_12M)\r
	117	begin\r
	118	W_LDn <= WB_LDn;\r
	119	W_CNTRLDn <= WB_CNTRLDn;\r
	120	W_CNTRCLRn <= WB_CNTRCLRn;\r
	121	W_COLLn <= WB_COLLn;\r
	122	W_VPLn <= WB_VPLn;\r
	123	W_OBJDATALn <= WB_OBJDATALn;\r
	124	W_MLDn <= WB_MLDn;\r
	125	W_SLDn <= WB_SLDn;\r
	126	end\r
	127	\r
	128	mc_ld_pls LD_PLS(\r
	129	\r
	130	.I_CLK_6M(~I_CLK_6M),\r
	131	.I_H_CNT(I_H_CNT),\r
	132	.I_3D_DI(W_3D),\r
	133	\r
	134	.O_LDn(WB_LDn),\r
	135	.O_CNTRLDn(WB_CNTRLDn),\r
	136	.O_CNTRCLRn(WB_CNTRCLRn),\r
	137	.O_COLLn(WB_COLLn),\r
	138	.O_VPLn(WB_VPLn),\r
	139	.O_OBJDATALn(WB_OBJDATALn),\r
	140	.O_MLDn(WB_MLDn),\r
	141	.O_SLDn(WB_SLDn)\r
	142	\r
	143	);\r
	144	\r
	145	wire W_H_FLIP1 = ~I_H_CNT[8]&I_H_FLIP;\r
	146	\r
	147	wire [7:3]W_HF_CNT = I_H_CNT[7:3]^{5{W_H_FLIP1}};\r
	148	wire [7:0]W_VF_CNT = I_V_CNT[7:0]^{8{I_V_FLIP}};\r
	149	\r
	150	assign O_8HF = W_HF_CNT[3];\r
	151	assign O_1VF = W_VF_CNT[0];\r
	152	\r
	153	reg [7:0]W_OBJ_D;\r
	154	wire [3:0]W_6J_DA = {I_H_FLIP , W_HF_CNT[7],W_HF_CNT[3],I_H_CNT[2]};\r
	155	wire [3:0]W_6J_DB = {W_OBJ_D[6],W_HF_CNT[3]&I_H_CNT[1], I_H_CNT[2],I_H_CNT[1]};\r
	156	wire [3:0]W_6J_Q = I_H_CNT[8] ? W_6J_DB:W_6J_DA;\r
	157	\r
	158	wire W_H_FLIP2 = W_6J_Q[3];\r
	159	// Prats 4F,5F\r
	160	wire [7:0]W_OBJ_RAM_AB = {1'b0,I_H_CNT[8],W_6J_Q[2],W_HF_CNT[6:4],W_6J_Q[1:0]};\r
	161	wire [7:0]W_OBJ_RAM_A = I_OBJ_RAM_RQn ? W_OBJ_RAM_AB: I_A[7:0] ;\r
	162	\r
	163	wire [7:0]W_OBJ_RAM_DOA,W_OBJ_RAM_DOB;\r
	164	\r
	165	reg [7:0]W_H_POSI;\r
	166	always@(posedge I_CLK_12M) W_H_POSI <= W_OBJ_RAM_DOB;\r
	167	\r
	168	mc_obj_ram OBJ_RAM(\r
	169	\r
	170	.I_CLKA(I_CLK_12M),\r
	171	.I_ADDRA(I_A[7:0]),\r
	172	.I_WEA(~I_OBJ_RAM_WRn),\r
	173	.I_CEA(~I_OBJ_RAM_RQn),\r
	174	.I_DA(I_BD),\r
	175	.O_DA(W_OBJ_RAM_DOA),\r
	176	\r
	177	.I_CLKB(I_CLK_12M),\r
	178	.I_ADDRB(W_OBJ_RAM_AB),\r
	179	.I_WEB(1'b0),\r
	180	.I_CEB(1'b1),\r
	181	.I_DB(8'h00),\r
	182	.O_DB(W_OBJ_RAM_DOB)\r
	183	\r
	184	);\r
	185	\r
	186	wire [7:0]W_OBJ_RAM_D = I_OBJ_RAM_RDn ? 8'h00: W_OBJ_RAM_DOA;\r
	187	// Prats 4L\r
	188	always@(posedge W_OBJDATALn) W_OBJ_D <= W_H_POSI; \r
	189	// Prats 4,5N\r
	190	\r
	191	wire [8:0]W_45N_Q = W_VF_CNT[7:0] + W_H_POSI ;\r
	192	assign W_3D = ~(&W_45N_Q[7:0]); \r
	193	\r
	194	reg [7:0]W_2M_Q;\r
	195	always@(posedge W_VPLn or negedge I_V_BLn)\r
	196	begin\r
	197	if(I_V_BLn==1'b0)\r
	198	W_2M_Q <= 0;\r
	199	else\r
	200	W_2M_Q <= W_45N_Q[7:0];\r
	201	end\r
	202	\r
	203	wire W_2N = I_H_CNT[8]&W_OBJ_D[7];\r
	204	wire [3:0]W_1M = W_2M_Q[3:0]^{W_2N,W_2N,W_2N,W_2N};\r
	205	\r
	206	wire W_VID_RAM_CSn = I_VID_RAM_RDn & I_VID_RAM_WRn;\r
	207	\r
	208	wire [7:0]W_VID_RAM_DI = I_VID_RAM_WRn ? 8'h00 : I_BD ;\r
	209	wire [7:0]W_VID_RAM_DOA;\r
	210	\r
	211	wire [11:0]W_VID_RAM_AA = {~(&W_2M_Q[7:4]),W_VID_RAM_CSn, 10'h00 /I_A[9:0]/};\r
	212	wire [11:0]W_VID_RAM_AB = { 1'b0, 1'b0,W_2M_Q[7:4],W_1M[3],W_HF_CNT[7:3]};\r
	213	\r
	214	wire [11:0]W_VID_RAM_A = I_C_BLn ? W_VID_RAM_AB:W_VID_RAM_AA;\r
	215	\r
	216	wire [7:0]W_VID_RAM_D = I_VID_RAM_RDn ? 8'h00 :W_VID_RAM_DOA;\r
	217	\r
	218	wire [7:0]W_VID_RAM_DOB;\r
	219	\r
	220	mc_vid_ram VID_RAM(\r
	221	\r
	222	.I_CLKA(I_CLK_12M),\r
	223	.I_ADDRA(I_A[9:0]),\r
	224	.I_DA(W_VID_RAM_DI),\r
	225	.I_WEA(~I_VID_RAM_WRn),\r
	226	.I_CEA(~W_VID_RAM_CSn),\r
	227	.O_DA(W_VID_RAM_DOA),\r
	228	\r
	229	.I_CLKB(I_CLK_12M),\r
	230	.I_ADDRB(W_VID_RAM_A[9:0]),\r
	231	.I_DB(8'h00),\r
	232	.I_WEB(1'b0),\r
	233	.I_CEB(1'b1),\r
	234	.O_DB(W_VID_RAM_DOB)\r
	235	\r
	236	);\r
	237	//-- VIDEO DATA OUTPUT --------------\r
	238	assign O_BD = W_OBJ_RAM_D \| W_VID_RAM_D;\r
	239	\r
	240	wire W_SRLD = ~(W_LDn \| W_VID_RAM_A[11]);\r
	241	\r
	242	wire [7:0]W_OBJ_ROM_AB = {W_OBJ_D[5:0],W_1M[3],W_OBJ_D[6]^I_H_CNT[3]};\r
	243	\r
	244	wire [7:0]W_OBJ_ROM_A = I_H_CNT[8] ? W_OBJ_ROM_AB: W_VID_RAM_DOB;\r
	245	\r
	246	assign O_OBJ_ROM_A = {W_OBJ_ROM_A,W_1M[2:0]};\r
	247	\r
	248	wire [7:0]W_1K_D = I_OBJ_ROM_A_D;\r
	249	wire [7:0]W_1H_D = I_OBJ_ROM_B_D;\r
	250	\r
	251	//---------------------------------------------------------------------------------\r
	252	wire W_2L_Qa,W_2K_Qd;\r
	253	wire W_2J_Qa,W_2H_Qd;\r
	254	wire W_H_FLIP2X;\r
	255	\r
	256	wire [3:0]W_3L_A = {W_2J_Qa,W_2L_Qa, 1'b1,W_SRLD};\r
	257	wire [3:0]W_3L_B = {W_2H_Qd,W_2K_Qd,W_SRLD, 1'b1}; \r
	258	wire [3:0]W_3L_Y = W_H_FLIP2X ? W_3L_B: W_3L_A; // [3]=RAW1,[2]=RAW0\r
	259	\r
	260	wire W_RAW0 = W_3L_Y[2];\r
	261	wire W_RAW1 = W_3L_Y[3];\r
	262	\r
	263	wire W_SRCLK = I_CLK_6M;\r
	264	//------ PARTS 2KL ---------------------------------------------- \r
	265	wire [1:0]C_2KL = W_3L_Y[1:0];\r
	266	wire [7:0]I_2KL = W_1K_D;\r
	267	reg [7:0]reg_2KL;\r
	268	\r
	269	assign W_2L_Qa = reg_2KL[7];\r
	270	assign W_2K_Qd = reg_2KL[0];\r
	271	always@(posedge W_SRCLK)\r
	272	begin\r
	273	case(C_2KL)\r
	274	2'b00: reg_2KL <= reg_2KL;\r
	275	2'b10: reg_2KL <= {reg_2KL[6:0],1'b0};\r
	276	2'b01: reg_2KL <= {1'b0,reg_2KL[7:1]};\r
	277	2'b11: reg_2KL <= I_2KL;\r
	278	endcase\r
	279	end\r
	280	//------ PARTS 2HJ ---------------------------------------------- \r
	281	wire [1:0]C_2HJ = W_3L_Y[1:0];\r
	282	wire [7:0]I_2HJ = W_1H_D;\r
	283	reg [7:0]reg_2HJ;\r
	284	\r
	285	assign W_2J_Qa = reg_2HJ[7];\r
	286	assign W_2H_Qd = reg_2HJ[0];\r
	287	always@(posedge W_SRCLK)\r
	288	begin\r
	289	case(C_2HJ)\r
	290	2'b00: reg_2HJ <= reg_2HJ;\r
	291	2'b10: reg_2HJ <= {reg_2HJ[6:0],1'b0};\r
	292	2'b01: reg_2HJ <= {1'b0,reg_2HJ[7:1]};\r
	293	2'b11: reg_2HJ <= I_2HJ;\r
	294	endcase\r
	295	end\r
	296	\r
	297	//----- SHT2 -----------------------------------------------------\r
	298	// Prats 6K\r
	299	reg [2:0]W_6K_Q;\r
	300	always@(posedge W_COLLn) W_6K_Q <= W_H_POSI[2:0];\r
	301	\r
	302	// Prats 6P\r
	303	reg [6:0]W_6P_Q;\r
	304	always@(posedge I_CLK_6M)\r
	305	begin\r
	306	if(W_LDn==1'b0) W_6P_Q <= {W_H_FLIP2,W_H_FLIP1,I_C_BLn,~I_H_CNT[8],W_6K_Q[2:0]};\r
	307	else W_6P_Q <= W_6P_Q;\r
	308	end\r
	309	\r
	310	assign W_H_FLIP2X = W_6P_Q[6];\r
	311	wire W_H_FLIP1X = W_6P_Q[5];\r
	312	wire W_C_BLnX = W_6P_Q[4];\r
	313	wire W_256HnX = W_6P_Q[3];\r
	314	wire [2:0]W_CD = W_6P_Q[2:0];\r
	315	\r
	316	assign O_256HnX = W_256HnX;\r
	317	assign O_C_BLnX = W_C_BLnX;\r
	318	\r
	319	wire W_45T_CLR = W_CNTRCLRn \| W_256HnX ;\r
	320	reg [7:0]W_45T_Q;\r
	321	\r
	322	always@(posedge I_CLK_6M)\r
	323	begin\r
	324	if(W_45T_CLR==1'b0)\r
	325	W_45T_Q <= 0;\r
	326	else if(W_CNTRLDn==1'b0)\r
	327	W_45T_Q <= W_H_POSI;\r
	328	else\r
	329	W_45T_Q <= W_45T_Q + 1;\r
	330	end\r
	331	\r
	332	wire [7:0]W_LRAM_A = W_45T_Q^{8{W_H_FLIP1X}};\r
	333	wire W_LRAM_WE = ~I_CLK_6M;\r
	334	\r
	335	wire [4:0]W_LRAM_DI;\r
	336	wire [4:0]W_LRAM_DO;\r
	337	\r
	338	reg [1:0]W_RV;\r
	339	reg [2:0]W_RC;\r
	340	wire W_1U_CLK = ~I_CLK_6M;\r
	341	\r
	342	always@(posedge W_1U_CLK)\r
	343	begin\r
	344	W_RV <= W_LRAM_DO[1:0]; \r
	345	W_RC <= W_LRAM_DO[4:2];\r
	346	end\r
	347	\r
	348	wire W_LRAM_AND = ~(~((W_LRAM_A[4]\|W_LRAM_A[5])\|(W_LRAM_A[6]\|W_LRAM_A[7]))\|W_256HnX );\r
	349	wire W_RAW_OR = W_RAW0 \| W_RAW1 ;\r
	350	\r
	351	wire [1:0]W_VID;\r
	352	wire [2:0]W_COL;\r
	353	\r
	354	assign W_VID[0] = ~(~(W_RAW0&W_RV[1])&W_RV[0]);\r
	355	assign W_VID[1] = ~(~(W_RAW1&W_RV[0])&W_RV[1]);\r
	356	assign W_COL[0] = ~(~(W_RAW_OR&W_CD[0]&W_RC[1]&W_RC[2])&W_RC[0]);\r
	357	assign W_COL[1] = ~(~(W_RAW_OR&W_CD[1]&W_RC[2]&W_RC[0])&W_RC[1]);\r
	358	assign W_COL[2] = ~(~(W_RAW_OR&W_CD[2]&W_RC[0]&W_RC[1])&W_RC[2]);\r
	359	\r
	360	assign O_VID = W_VID;\r
	361	assign O_COL = W_COL;\r
	362	\r
	363	assign W_LRAM_DI[0] = W_LRAM_AND&W_VID[0];\r
	364	assign W_LRAM_DI[1] = W_LRAM_AND&W_VID[1]; \r
	365	assign W_LRAM_DI[2] = W_LRAM_AND&W_COL[0];\r
	366	assign W_LRAM_DI[3] = W_LRAM_AND&W_COL[1];\r
	367	assign W_LRAM_DI[4] = W_LRAM_AND&W_COL[2];\r
	368	\r
	369	mc_lram LRAM(\r
	370	\r
	371	.I_CLK(I_CLK_18M),\r
	372	.I_ADDR(W_LRAM_A),\r
	373	.I_WE(W_LRAM_WE),\r
	374	.I_D(W_LRAM_DI),\r
	375	.O_Dn(W_LRAM_DO)\r
	376	\r
	377	);\r
	378	\r
	379	mc_missile MISSILE(\r
	380	\r
	381	.I_CLK_18M(I_CLK_18M),\r
	382	.I_CLK_6M(I_CLK_6M),\r
	383	.I_C_BLn_X(W_C_BLnX),\r
	384	.I_MLDn(W_MLDn),\r
	385	.I_SLDn(W_SLDn),\r
	386	.I_HPOS(W_H_POSI),\r
	387	\r
	388	.O_MISSILEn(O_MISSILEn),\r
	389	.O_SHELLn(O_SHELLn)\r
	390	\r
	391	);\r
	392	\r
	393	endmodule\r
	394	\r
	395	\r