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[fpga-games] / galaxian / t80_ip / T80_MCode.vhd
1 --
2 -- Z80 compatible microprocessor core
3 --
4 -- Version : 0242
5 --
6 -- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
7 --
8 -- All rights reserved
9 --
10 -- Redistribution and use in source and synthezised forms, with or without
11 -- modification, are permitted provided that the following conditions are met:
12 --
13 -- Redistributions of source code must retain the above copyright notice,
14 -- this list of conditions and the following disclaimer.
15 --
16 -- Redistributions in synthesized form must reproduce the above copyright
17 -- notice, this list of conditions and the following disclaimer in the
18 -- documentation and/or other materials provided with the distribution.
19 --
20 -- Neither the name of the author nor the names of other contributors may
21 -- be used to endorse or promote products derived from this software without
22 -- specific prior written permission.
23 --
24 -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
28 -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 -- POSSIBILITY OF SUCH DAMAGE.
35 --
36 -- Please report bugs to the author, but before you do so, please
37 -- make sure that this is not a derivative work and that
38 -- you have the latest version of this file.
39 --
40 -- The latest version of this file can be found at:
41 -- http://www.opencores.org/cvsweb.shtml/t80/
42 --
43 -- Limitations :
44 --
45 -- File history :
46 --
47 -- 0208 : First complete release
48 --
49 -- 0211 : Fixed IM 1
50 --
51 -- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
52 --
53 -- 0235 : Added IM 2 fix by Mike Johnson
54 --
55 -- 0238 : Added NoRead signal
56 --
57 -- 0238b: Fixed instruction timing for POP and DJNZ
58 --
59 -- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
60 --
61 -- 0242 : Fixed I/O instruction timing, cleanup
62 --
63
64 library IEEE;
65 use IEEE.std_logic_1164.all;
66 use IEEE.numeric_std.all;
67
68 entity T80_MCode is
69 generic(
70 Mode : integer := 0;
71 Flag_C : integer := 0;
72 Flag_N : integer := 1;
73 Flag_P : integer := 2;
74 Flag_X : integer := 3;
75 Flag_H : integer := 4;
76 Flag_Y : integer := 5;
77 Flag_Z : integer := 6;
78 Flag_S : integer := 7
79 );
80 port(
81 IR : in std_logic_vector(7 downto 0);
82 ISet : in std_logic_vector(1 downto 0);
83 MCycle : in std_logic_vector(2 downto 0);
84 F : in std_logic_vector(7 downto 0);
85 NMICycle : in std_logic;
86 IntCycle : in std_logic;
87 MCycles : out std_logic_vector(2 downto 0);
88 TStates : out std_logic_vector(2 downto 0);
89 Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
90 Inc_PC : out std_logic;
91 Inc_WZ : out std_logic;
92 IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
93 Read_To_Reg : out std_logic;
94 Read_To_Acc : out std_logic;
95 Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
96 Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
97 ALU_Op : out std_logic_vector(3 downto 0);
98 -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
99 Save_ALU : out std_logic;
100 PreserveC : out std_logic;
101 Arith16 : out std_logic;
102 Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
103 IORQ : out std_logic;
104 Jump : out std_logic;
105 JumpE : out std_logic;
106 JumpXY : out std_logic;
107 Call : out std_logic;
108 RstP : out std_logic;
109 LDZ : out std_logic;
110 LDW : out std_logic;
111 LDSPHL : out std_logic;
112 Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
113 ExchangeDH : out std_logic;
114 ExchangeRp : out std_logic;
115 ExchangeAF : out std_logic;
116 ExchangeRS : out std_logic;
117 I_DJNZ : out std_logic;
118 I_CPL : out std_logic;
119 I_CCF : out std_logic;
120 I_SCF : out std_logic;
121 I_RETN : out std_logic;
122 I_BT : out std_logic;
123 I_BC : out std_logic;
124 I_BTR : out std_logic;
125 I_RLD : out std_logic;
126 I_RRD : out std_logic;
127 I_INRC : out std_logic;
128 SetDI : out std_logic;
129 SetEI : out std_logic;
130 IMode : out std_logic_vector(1 downto 0);
131 Halt : out std_logic;
132 NoRead : out std_logic;
133 Write : out std_logic
134 );
135 end T80_MCode;
136
137 architecture rtl of T80_MCode is
138
139 constant aNone : std_logic_vector(2 downto 0) := "111";
140 constant aBC : std_logic_vector(2 downto 0) := "000";
141 constant aDE : std_logic_vector(2 downto 0) := "001";
142 constant aXY : std_logic_vector(2 downto 0) := "010";
143 constant aIOA : std_logic_vector(2 downto 0) := "100";
144 constant aSP : std_logic_vector(2 downto 0) := "101";
145 constant aZI : std_logic_vector(2 downto 0) := "110";
146 -- constant aNone : std_logic_vector(2 downto 0) := "000";
147 -- constant aXY : std_logic_vector(2 downto 0) := "001";
148 -- constant aIOA : std_logic_vector(2 downto 0) := "010";
149 -- constant aSP : std_logic_vector(2 downto 0) := "011";
150 -- constant aBC : std_logic_vector(2 downto 0) := "100";
151 -- constant aDE : std_logic_vector(2 downto 0) := "101";
152 -- constant aZI : std_logic_vector(2 downto 0) := "110";
153
154 function is_cc_true(
155 F : std_logic_vector(7 downto 0);
156 cc : bit_vector(2 downto 0)
157 ) return boolean is
158 begin
159 if Mode = 3 then
160 case cc is
161 when "000" => return F(7) = '0'; -- NZ
162 when "001" => return F(7) = '1'; -- Z
163 when "010" => return F(4) = '0'; -- NC
164 when "011" => return F(4) = '1'; -- C
165 when "100" => return false;
166 when "101" => return false;
167 when "110" => return false;
168 when "111" => return false;
169 end case;
170 else
171 case cc is
172 when "000" => return F(6) = '0'; -- NZ
173 when "001" => return F(6) = '1'; -- Z
174 when "010" => return F(0) = '0'; -- NC
175 when "011" => return F(0) = '1'; -- C
176 when "100" => return F(2) = '0'; -- PO
177 when "101" => return F(2) = '1'; -- PE
178 when "110" => return F(7) = '0'; -- P
179 when "111" => return F(7) = '1'; -- M
180 end case;
181 end if;
182 end;
183
184 begin
185
186 process (IR, ISet, MCycle, F, NMICycle, IntCycle)
187 variable DDD : std_logic_vector(2 downto 0);
188 variable SSS : std_logic_vector(2 downto 0);
189 variable DPair : std_logic_vector(1 downto 0);
190 variable IRB : bit_vector(7 downto 0);
191 begin
192 DDD := IR(5 downto 3);
193 SSS := IR(2 downto 0);
194 DPair := IR(5 downto 4);
195 IRB := to_bitvector(IR);
196
197 MCycles <= "001";
198 if MCycle = "001" then
199 TStates <= "100";
200 else
201 TStates <= "011";
202 end if;
203 Prefix <= "00";
204 Inc_PC <= '0';
205 Inc_WZ <= '0';
206 IncDec_16 <= "0000";
207 Read_To_Acc <= '0';
208 Read_To_Reg <= '0';
209 Set_BusB_To <= "0000";
210 Set_BusA_To <= "0000";
211 ALU_Op <= "0" & IR(5 downto 3);
212 Save_ALU <= '0';
213 PreserveC <= '0';
214 Arith16 <= '0';
215 IORQ <= '0';
216 Set_Addr_To <= aNone;
217 Jump <= '0';
218 JumpE <= '0';
219 JumpXY <= '0';
220 Call <= '0';
221 RstP <= '0';
222 LDZ <= '0';
223 LDW <= '0';
224 LDSPHL <= '0';
225 Special_LD <= "000";
226 ExchangeDH <= '0';
227 ExchangeRp <= '0';
228 ExchangeAF <= '0';
229 ExchangeRS <= '0';
230 I_DJNZ <= '0';
231 I_CPL <= '0';
232 I_CCF <= '0';
233 I_SCF <= '0';
234 I_RETN <= '0';
235 I_BT <= '0';
236 I_BC <= '0';
237 I_BTR <= '0';
238 I_RLD <= '0';
239 I_RRD <= '0';
240 I_INRC <= '0';
241 SetDI <= '0';
242 SetEI <= '0';
243 IMode <= "11";
244 Halt <= '0';
245 NoRead <= '0';
246 Write <= '0';
247
248 case ISet is
249 when "00" =>
250
251 ------------------------------------------------------------------------------
252 --
253 -- Unprefixed instructions
254 --
255 ------------------------------------------------------------------------------
256
257 case IRB is
258 -- 8 BIT LOAD GROUP
259 when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
260 |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
261 |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
262 |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
263 |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
264 |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
265 |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
266 -- LD r,r'
267 Set_BusB_To(2 downto 0) <= SSS;
268 ExchangeRp <= '1';
269 Set_BusA_To(2 downto 0) <= DDD;
270 Read_To_Reg <= '1';
271 when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
272 -- LD r,n
273 MCycles <= "010";
274 case to_integer(unsigned(MCycle)) is
275 when 2 =>
276 Inc_PC <= '1';
277 Set_BusA_To(2 downto 0) <= DDD;
278 Read_To_Reg <= '1';
279 when others => null;
280 end case;
281 when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
282 -- LD r,(HL)
283 MCycles <= "010";
284 case to_integer(unsigned(MCycle)) is
285 when 1 =>
286 Set_Addr_To <= aXY;
287 when 2 =>
288 Set_BusA_To(2 downto 0) <= DDD;
289 Read_To_Reg <= '1';
290 when others => null;
291 end case;
292 when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
293 -- LD (HL),r
294 MCycles <= "010";
295 case to_integer(unsigned(MCycle)) is
296 when 1 =>
297 Set_Addr_To <= aXY;
298 Set_BusB_To(2 downto 0) <= SSS;
299 Set_BusB_To(3) <= '0';
300 when 2 =>
301 Write <= '1';
302 when others => null;
303 end case;
304 when "00110110" =>
305 -- LD (HL),n
306 MCycles <= "011";
307 case to_integer(unsigned(MCycle)) is
308 when 2 =>
309 Inc_PC <= '1';
310 Set_Addr_To <= aXY;
311 Set_BusB_To(2 downto 0) <= SSS;
312 Set_BusB_To(3) <= '0';
313 when 3 =>
314 Write <= '1';
315 when others => null;
316 end case;
317 when "00001010" =>
318 -- LD A,(BC)
319 MCycles <= "010";
320 case to_integer(unsigned(MCycle)) is
321 when 1 =>
322 Set_Addr_To <= aBC;
323 when 2 =>
324 Read_To_Acc <= '1';
325 when others => null;
326 end case;
327 when "00011010" =>
328 -- LD A,(DE)
329 MCycles <= "010";
330 case to_integer(unsigned(MCycle)) is
331 when 1 =>
332 Set_Addr_To <= aDE;
333 when 2 =>
334 Read_To_Acc <= '1';
335 when others => null;
336 end case;
337 when "00111010" =>
338 if Mode = 3 then
339 -- LDD A,(HL)
340 MCycles <= "010";
341 case to_integer(unsigned(MCycle)) is
342 when 1 =>
343 Set_Addr_To <= aXY;
344 when 2 =>
345 Read_To_Acc <= '1';
346 IncDec_16 <= "1110";
347 when others => null;
348 end case;
349 else
350 -- LD A,(nn)
351 MCycles <= "100";
352 case to_integer(unsigned(MCycle)) is
353 when 2 =>
354 Inc_PC <= '1';
355 LDZ <= '1';
356 when 3 =>
357 Set_Addr_To <= aZI;
358 Inc_PC <= '1';
359 when 4 =>
360 Read_To_Acc <= '1';
361 when others => null;
362 end case;
363 end if;
364 when "00000010" =>
365 -- LD (BC),A
366 MCycles <= "010";
367 case to_integer(unsigned(MCycle)) is
368 when 1 =>
369 Set_Addr_To <= aBC;
370 Set_BusB_To <= "0111";
371 when 2 =>
372 Write <= '1';
373 when others => null;
374 end case;
375 when "00010010" =>
376 -- LD (DE),A
377 MCycles <= "010";
378 case to_integer(unsigned(MCycle)) is
379 when 1 =>
380 Set_Addr_To <= aDE;
381 Set_BusB_To <= "0111";
382 when 2 =>
383 Write <= '1';
384 when others => null;
385 end case;
386 when "00110010" =>
387 if Mode = 3 then
388 -- LDD (HL),A
389 MCycles <= "010";
390 case to_integer(unsigned(MCycle)) is
391 when 1 =>
392 Set_Addr_To <= aXY;
393 Set_BusB_To <= "0111";
394 when 2 =>
395 Write <= '1';
396 IncDec_16 <= "1110";
397 when others => null;
398 end case;
399 else
400 -- LD (nn),A
401 MCycles <= "100";
402 case to_integer(unsigned(MCycle)) is
403 when 2 =>
404 Inc_PC <= '1';
405 LDZ <= '1';
406 when 3 =>
407 Set_Addr_To <= aZI;
408 Inc_PC <= '1';
409 Set_BusB_To <= "0111";
410 when 4 =>
411 Write <= '1';
412 when others => null;
413 end case;
414 end if;
415
416 -- 16 BIT LOAD GROUP
417 when "00000001"|"00010001"|"00100001"|"00110001" =>
418 -- LD dd,nn
419 MCycles <= "011";
420 case to_integer(unsigned(MCycle)) is
421 when 2 =>
422 Inc_PC <= '1';
423 Read_To_Reg <= '1';
424 if DPAIR = "11" then
425 Set_BusA_To(3 downto 0) <= "1000";
426 else
427 Set_BusA_To(2 downto 1) <= DPAIR;
428 Set_BusA_To(0) <= '1';
429 end if;
430 when 3 =>
431 Inc_PC <= '1';
432 Read_To_Reg <= '1';
433 if DPAIR = "11" then
434 Set_BusA_To(3 downto 0) <= "1001";
435 else
436 Set_BusA_To(2 downto 1) <= DPAIR;
437 Set_BusA_To(0) <= '0';
438 end if;
439 when others => null;
440 end case;
441 when "00101010" =>
442 if Mode = 3 then
443 -- LDI A,(HL)
444 MCycles <= "010";
445 case to_integer(unsigned(MCycle)) is
446 when 1 =>
447 Set_Addr_To <= aXY;
448 when 2 =>
449 Read_To_Acc <= '1';
450 IncDec_16 <= "0110";
451 when others => null;
452 end case;
453 else
454 -- LD HL,(nn)
455 MCycles <= "101";
456 case to_integer(unsigned(MCycle)) is
457 when 2 =>
458 Inc_PC <= '1';
459 LDZ <= '1';
460 when 3 =>
461 Set_Addr_To <= aZI;
462 Inc_PC <= '1';
463 LDW <= '1';
464 when 4 =>
465 Set_BusA_To(2 downto 0) <= "101"; -- L
466 Read_To_Reg <= '1';
467 Inc_WZ <= '1';
468 Set_Addr_To <= aZI;
469 when 5 =>
470 Set_BusA_To(2 downto 0) <= "100"; -- H
471 Read_To_Reg <= '1';
472 when others => null;
473 end case;
474 end if;
475 when "00100010" =>
476 if Mode = 3 then
477 -- LDI (HL),A
478 MCycles <= "010";
479 case to_integer(unsigned(MCycle)) is
480 when 1 =>
481 Set_Addr_To <= aXY;
482 Set_BusB_To <= "0111";
483 when 2 =>
484 Write <= '1';
485 IncDec_16 <= "0110";
486 when others => null;
487 end case;
488 else
489 -- LD (nn),HL
490 MCycles <= "101";
491 case to_integer(unsigned(MCycle)) is
492 when 2 =>
493 Inc_PC <= '1';
494 LDZ <= '1';
495 when 3 =>
496 Set_Addr_To <= aZI;
497 Inc_PC <= '1';
498 LDW <= '1';
499 Set_BusB_To <= "0101"; -- L
500 when 4 =>
501 Inc_WZ <= '1';
502 Set_Addr_To <= aZI;
503 Write <= '1';
504 Set_BusB_To <= "0100"; -- H
505 when 5 =>
506 Write <= '1';
507 when others => null;
508 end case;
509 end if;
510 when "11111001" =>
511 -- LD SP,HL
512 TStates <= "110";
513 LDSPHL <= '1';
514 when "11000101"|"11010101"|"11100101"|"11110101" =>
515 -- PUSH qq
516 MCycles <= "011";
517 case to_integer(unsigned(MCycle)) is
518 when 1 =>
519 TStates <= "101";
520 IncDec_16 <= "1111";
521 Set_Addr_TO <= aSP;
522 if DPAIR = "11" then
523 Set_BusB_To <= "0111";
524 else
525 Set_BusB_To(2 downto 1) <= DPAIR;
526 Set_BusB_To(0) <= '0';
527 Set_BusB_To(3) <= '0';
528 end if;
529 when 2 =>
530 IncDec_16 <= "1111";
531 Set_Addr_To <= aSP;
532 if DPAIR = "11" then
533 Set_BusB_To <= "1011";
534 else
535 Set_BusB_To(2 downto 1) <= DPAIR;
536 Set_BusB_To(0) <= '1';
537 Set_BusB_To(3) <= '0';
538 end if;
539 Write <= '1';
540 when 3 =>
541 Write <= '1';
542 when others => null;
543 end case;
544 when "11000001"|"11010001"|"11100001"|"11110001" =>
545 -- POP qq
546 MCycles <= "011";
547 case to_integer(unsigned(MCycle)) is
548 when 1 =>
549 Set_Addr_To <= aSP;
550 when 2 =>
551 IncDec_16 <= "0111";
552 Set_Addr_To <= aSP;
553 Read_To_Reg <= '1';
554 if DPAIR = "11" then
555 Set_BusA_To(3 downto 0) <= "1011";
556 else
557 Set_BusA_To(2 downto 1) <= DPAIR;
558 Set_BusA_To(0) <= '1';
559 end if;
560 when 3 =>
561 IncDec_16 <= "0111";
562 Read_To_Reg <= '1';
563 if DPAIR = "11" then
564 Set_BusA_To(3 downto 0) <= "0111";
565 else
566 Set_BusA_To(2 downto 1) <= DPAIR;
567 Set_BusA_To(0) <= '0';
568 end if;
569 when others => null;
570 end case;
571
572 -- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
573 when "11101011" =>
574 if Mode /= 3 then
575 -- EX DE,HL
576 ExchangeDH <= '1';
577 end if;
578 when "00001000" =>
579 if Mode = 3 then
580 -- LD (nn),SP
581 MCycles <= "101";
582 case to_integer(unsigned(MCycle)) is
583 when 2 =>
584 Inc_PC <= '1';
585 LDZ <= '1';
586 when 3 =>
587 Set_Addr_To <= aZI;
588 Inc_PC <= '1';
589 LDW <= '1';
590 Set_BusB_To <= "1000";
591 when 4 =>
592 Inc_WZ <= '1';
593 Set_Addr_To <= aZI;
594 Write <= '1';
595 Set_BusB_To <= "1001";
596 when 5 =>
597 Write <= '1';
598 when others => null;
599 end case;
600 elsif Mode < 2 then
601 -- EX AF,AF'
602 ExchangeAF <= '1';
603 end if;
604 when "11011001" =>
605 if Mode = 3 then
606 -- RETI
607 MCycles <= "011";
608 case to_integer(unsigned(MCycle)) is
609 when 1 =>
610 Set_Addr_TO <= aSP;
611 when 2 =>
612 IncDec_16 <= "0111";
613 Set_Addr_To <= aSP;
614 LDZ <= '1';
615 when 3 =>
616 Jump <= '1';
617 IncDec_16 <= "0111";
618 I_RETN <= '1';
619 SetEI <= '1';
620 when others => null;
621 end case;
622 elsif Mode < 2 then
623 -- EXX
624 ExchangeRS <= '1';
625 end if;
626 when "11100011" =>
627 if Mode /= 3 then
628 -- EX (SP),HL
629 MCycles <= "101";
630 case to_integer(unsigned(MCycle)) is
631 when 1 =>
632 Set_Addr_To <= aSP;
633 when 2 =>
634 Read_To_Reg <= '1';
635 Set_BusA_To <= "0101";
636 Set_BusB_To <= "0101";
637 Set_Addr_To <= aSP;
638 when 3 =>
639 IncDec_16 <= "0111";
640 Set_Addr_To <= aSP;
641 TStates <= "100";
642 Write <= '1';
643 when 4 =>
644 Read_To_Reg <= '1';
645 Set_BusA_To <= "0100";
646 Set_BusB_To <= "0100";
647 Set_Addr_To <= aSP;
648 when 5 =>
649 IncDec_16 <= "1111";
650 TStates <= "101";
651 Write <= '1';
652 when others => null;
653 end case;
654 end if;
655
656 -- 8 BIT ARITHMETIC AND LOGICAL GROUP
657 when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
658 |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
659 |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
660 |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
661 |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
662 |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
663 |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
664 |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
665 -- ADD A,r
666 -- ADC A,r
667 -- SUB A,r
668 -- SBC A,r
669 -- AND A,r
670 -- OR A,r
671 -- XOR A,r
672 -- CP A,r
673 Set_BusB_To(2 downto 0) <= SSS;
674 Set_BusA_To(2 downto 0) <= "111";
675 Read_To_Reg <= '1';
676 Save_ALU <= '1';
677 when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
678 -- ADD A,(HL)
679 -- ADC A,(HL)
680 -- SUB A,(HL)
681 -- SBC A,(HL)
682 -- AND A,(HL)
683 -- OR A,(HL)
684 -- XOR A,(HL)
685 -- CP A,(HL)
686 MCycles <= "010";
687 case to_integer(unsigned(MCycle)) is
688 when 1 =>
689 Set_Addr_To <= aXY;
690 when 2 =>
691 Read_To_Reg <= '1';
692 Save_ALU <= '1';
693 Set_BusB_To(2 downto 0) <= SSS;
694 Set_BusA_To(2 downto 0) <= "111";
695 when others => null;
696 end case;
697 when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
698 -- ADD A,n
699 -- ADC A,n
700 -- SUB A,n
701 -- SBC A,n
702 -- AND A,n
703 -- OR A,n
704 -- XOR A,n
705 -- CP A,n
706 MCycles <= "010";
707 if MCycle = "010" then
708 Inc_PC <= '1';
709 Read_To_Reg <= '1';
710 Save_ALU <= '1';
711 Set_BusB_To(2 downto 0) <= SSS;
712 Set_BusA_To(2 downto 0) <= "111";
713 end if;
714 when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
715 -- INC r
716 Set_BusB_To <= "1010";
717 Set_BusA_To(2 downto 0) <= DDD;
718 Read_To_Reg <= '1';
719 Save_ALU <= '1';
720 PreserveC <= '1';
721 ALU_Op <= "0000";
722 when "00110100" =>
723 -- INC (HL)
724 MCycles <= "011";
725 case to_integer(unsigned(MCycle)) is
726 when 1 =>
727 Set_Addr_To <= aXY;
728 when 2 =>
729 TStates <= "100";
730 Set_Addr_To <= aXY;
731 Read_To_Reg <= '1';
732 Save_ALU <= '1';
733 PreserveC <= '1';
734 ALU_Op <= "0000";
735 Set_BusB_To <= "1010";
736 Set_BusA_To(2 downto 0) <= DDD;
737 when 3 =>
738 Write <= '1';
739 when others => null;
740 end case;
741 when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
742 -- DEC r
743 Set_BusB_To <= "1010";
744 Set_BusA_To(2 downto 0) <= DDD;
745 Read_To_Reg <= '1';
746 Save_ALU <= '1';
747 PreserveC <= '1';
748 ALU_Op <= "0010";
749 when "00110101" =>
750 -- DEC (HL)
751 MCycles <= "011";
752 case to_integer(unsigned(MCycle)) is
753 when 1 =>
754 Set_Addr_To <= aXY;
755 when 2 =>
756 TStates <= "100";
757 Set_Addr_To <= aXY;
758 ALU_Op <= "0010";
759 Read_To_Reg <= '1';
760 Save_ALU <= '1';
761 PreserveC <= '1';
762 Set_BusB_To <= "1010";
763 Set_BusA_To(2 downto 0) <= DDD;
764 when 3 =>
765 Write <= '1';
766 when others => null;
767 end case;
768
769 -- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
770 when "00100111" =>
771 -- DAA
772 Set_BusA_To(2 downto 0) <= "111";
773 Read_To_Reg <= '1';
774 ALU_Op <= "1100";
775 Save_ALU <= '1';
776 when "00101111" =>
777 -- CPL
778 I_CPL <= '1';
779 when "00111111" =>
780 -- CCF
781 I_CCF <= '1';
782 when "00110111" =>
783 -- SCF
784 I_SCF <= '1';
785 when "00000000" =>
786 if NMICycle = '1' then
787 -- NMI
788 MCycles <= "011";
789 case to_integer(unsigned(MCycle)) is
790 when 1 =>
791 TStates <= "101";
792 IncDec_16 <= "1111";
793 Set_Addr_To <= aSP;
794 Set_BusB_To <= "1101";
795 when 2 =>
796 TStates <= "100";
797 Write <= '1';
798 IncDec_16 <= "1111";
799 Set_Addr_To <= aSP;
800 Set_BusB_To <= "1100";
801 when 3 =>
802 TStates <= "100";
803 Write <= '1';
804 when others => null;
805 end case;
806 elsif IntCycle = '1' then
807 -- INT (IM 2)
808 MCycles <= "101";
809 case to_integer(unsigned(MCycle)) is
810 when 1 =>
811 LDZ <= '1';
812 TStates <= "101";
813 IncDec_16 <= "1111";
814 Set_Addr_To <= aSP;
815 Set_BusB_To <= "1101";
816 when 2 =>
817 TStates <= "100";
818 Write <= '1';
819 IncDec_16 <= "1111";
820 Set_Addr_To <= aSP;
821 Set_BusB_To <= "1100";
822 when 3 =>
823 TStates <= "100";
824 Write <= '1';
825 when 4 =>
826 Inc_PC <= '1';
827 LDZ <= '1';
828 when 5 =>
829 Jump <= '1';
830 when others => null;
831 end case;
832 else
833 -- NOP
834 end if;
835 when "01110110" =>
836 -- HALT
837 Halt <= '1';
838 when "11110011" =>
839 -- DI
840 SetDI <= '1';
841 when "11111011" =>
842 -- EI
843 SetEI <= '1';
844
845 -- 16 BIT ARITHMETIC GROUP
846 when "00001001"|"00011001"|"00101001"|"00111001" =>
847 -- ADD HL,ss
848 MCycles <= "011";
849 case to_integer(unsigned(MCycle)) is
850 when 2 =>
851 NoRead <= '1';
852 ALU_Op <= "0000";
853 Read_To_Reg <= '1';
854 Save_ALU <= '1';
855 Set_BusA_To(2 downto 0) <= "101";
856 case to_integer(unsigned(IR(5 downto 4))) is
857 when 0|1|2 =>
858 Set_BusB_To(2 downto 1) <= IR(5 downto 4);
859 Set_BusB_To(0) <= '1';
860 when others =>
861 Set_BusB_To <= "1000";
862 end case;
863 TStates <= "100";
864 Arith16 <= '1';
865 when 3 =>
866 NoRead <= '1';
867 Read_To_Reg <= '1';
868 Save_ALU <= '1';
869 ALU_Op <= "0001";
870 Set_BusA_To(2 downto 0) <= "100";
871 case to_integer(unsigned(IR(5 downto 4))) is
872 when 0|1|2 =>
873 Set_BusB_To(2 downto 1) <= IR(5 downto 4);
874 when others =>
875 Set_BusB_To <= "1001";
876 end case;
877 Arith16 <= '1';
878 when others =>
879 end case;
880 when "00000011"|"00010011"|"00100011"|"00110011" =>
881 -- INC ss
882 TStates <= "110";
883 IncDec_16(3 downto 2) <= "01";
884 IncDec_16(1 downto 0) <= DPair;
885 when "00001011"|"00011011"|"00101011"|"00111011" =>
886 -- DEC ss
887 TStates <= "110";
888 IncDec_16(3 downto 2) <= "11";
889 IncDec_16(1 downto 0) <= DPair;
890
891 -- ROTATE AND SHIFT GROUP
892 when "00000111"
893 -- RLCA
894 |"00010111"
895 -- RLA
896 |"00001111"
897 -- RRCA
898 |"00011111" =>
899 -- RRA
900 Set_BusA_To(2 downto 0) <= "111";
901 ALU_Op <= "1000";
902 Read_To_Reg <= '1';
903 Save_ALU <= '1';
904
905 -- JUMP GROUP
906 when "11000011" =>
907 -- JP nn
908 MCycles <= "011";
909 case to_integer(unsigned(MCycle)) is
910 when 2 =>
911 Inc_PC <= '1';
912 LDZ <= '1';
913 when 3 =>
914 Inc_PC <= '1';
915 Jump <= '1';
916 when others => null;
917 end case;
918 when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
919 if IR(5) = '1' and Mode = 3 then
920 case IRB(4 downto 3) is
921 when "00" =>
922 -- LD ($FF00+C),A
923 MCycles <= "010";
924 case to_integer(unsigned(MCycle)) is
925 when 1 =>
926 Set_Addr_To <= aBC;
927 Set_BusB_To <= "0111";
928 when 2 =>
929 Write <= '1';
930 IORQ <= '1';
931 when others =>
932 end case;
933 when "01" =>
934 -- LD (nn),A
935 MCycles <= "100";
936 case to_integer(unsigned(MCycle)) is
937 when 2 =>
938 Inc_PC <= '1';
939 LDZ <= '1';
940 when 3 =>
941 Set_Addr_To <= aZI;
942 Inc_PC <= '1';
943 Set_BusB_To <= "0111";
944 when 4 =>
945 Write <= '1';
946 when others => null;
947 end case;
948 when "10" =>
949 -- LD A,($FF00+C)
950 MCycles <= "010";
951 case to_integer(unsigned(MCycle)) is
952 when 1 =>
953 Set_Addr_To <= aBC;
954 when 2 =>
955 Read_To_Acc <= '1';
956 IORQ <= '1';
957 when others =>
958 end case;
959 when "11" =>
960 -- LD A,(nn)
961 MCycles <= "100";
962 case to_integer(unsigned(MCycle)) is
963 when 2 =>
964 Inc_PC <= '1';
965 LDZ <= '1';
966 when 3 =>
967 Set_Addr_To <= aZI;
968 Inc_PC <= '1';
969 when 4 =>
970 Read_To_Acc <= '1';
971 when others => null;
972 end case;
973 end case;
974 else
975 -- JP cc,nn
976 MCycles <= "011";
977 case to_integer(unsigned(MCycle)) is
978 when 2 =>
979 Inc_PC <= '1';
980 LDZ <= '1';
981 when 3 =>
982 Inc_PC <= '1';
983 if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
984 Jump <= '1';
985 end if;
986 when others => null;
987 end case;
988 end if;
989 when "00011000" =>
990 if Mode /= 2 then
991 -- JR e
992 MCycles <= "011";
993 case to_integer(unsigned(MCycle)) is
994 when 2 =>
995 Inc_PC <= '1';
996 when 3 =>
997 NoRead <= '1';
998 JumpE <= '1';
999 TStates <= "101";
1000 when others => null;
1001 end case;
1002 end if;
1003 when "00111000" =>
1004 if Mode /= 2 then
1005 -- JR C,e
1006 MCycles <= "011";
1007 case to_integer(unsigned(MCycle)) is
1008 when 2 =>
1009 Inc_PC <= '1';
1010 if F(Flag_C) = '0' then
1011 MCycles <= "010";
1012 end if;
1013 when 3 =>
1014 NoRead <= '1';
1015 JumpE <= '1';
1016 TStates <= "101";
1017 when others => null;
1018 end case;
1019 end if;
1020 when "00110000" =>
1021 if Mode /= 2 then
1022 -- JR NC,e
1023 MCycles <= "011";
1024 case to_integer(unsigned(MCycle)) is
1025 when 2 =>
1026 Inc_PC <= '1';
1027 if F(Flag_C) = '1' then
1028 MCycles <= "010";
1029 end if;
1030 when 3 =>
1031 NoRead <= '1';
1032 JumpE <= '1';
1033 TStates <= "101";
1034 when others => null;
1035 end case;
1036 end if;
1037 when "00101000" =>
1038 if Mode /= 2 then
1039 -- JR Z,e
1040 MCycles <= "011";
1041 case to_integer(unsigned(MCycle)) is
1042 when 2 =>
1043 Inc_PC <= '1';
1044 if F(Flag_Z) = '0' then
1045 MCycles <= "010";
1046 end if;
1047 when 3 =>
1048 NoRead <= '1';
1049 JumpE <= '1';
1050 TStates <= "101";
1051 when others => null;
1052 end case;
1053 end if;
1054 when "00100000" =>
1055 if Mode /= 2 then
1056 -- JR NZ,e
1057 MCycles <= "011";
1058 case to_integer(unsigned(MCycle)) is
1059 when 2 =>
1060 Inc_PC <= '1';
1061 if F(Flag_Z) = '1' then
1062 MCycles <= "010";
1063 end if;
1064 when 3 =>
1065 NoRead <= '1';
1066 JumpE <= '1';
1067 TStates <= "101";
1068 when others => null;
1069 end case;
1070 end if;
1071 when "11101001" =>
1072 -- JP (HL)
1073 JumpXY <= '1';
1074 when "00010000" =>
1075 if Mode = 3 then
1076 I_DJNZ <= '1';
1077 elsif Mode < 2 then
1078 -- DJNZ,e
1079 MCycles <= "011";
1080 case to_integer(unsigned(MCycle)) is
1081 when 1 =>
1082 TStates <= "101";
1083 I_DJNZ <= '1';
1084 Set_BusB_To <= "1010";
1085 Set_BusA_To(2 downto 0) <= "000";
1086 Read_To_Reg <= '1';
1087 Save_ALU <= '1';
1088 ALU_Op <= "0010";
1089 when 2 =>
1090 I_DJNZ <= '1';
1091 Inc_PC <= '1';
1092 when 3 =>
1093 NoRead <= '1';
1094 JumpE <= '1';
1095 TStates <= "101";
1096 when others => null;
1097 end case;
1098 end if;
1099
1100 -- CALL AND RETURN GROUP
1101 when "11001101" =>
1102 -- CALL nn
1103 MCycles <= "101";
1104 case to_integer(unsigned(MCycle)) is
1105 when 2 =>
1106 Inc_PC <= '1';
1107 LDZ <= '1';
1108 when 3 =>
1109 IncDec_16 <= "1111";
1110 Inc_PC <= '1';
1111 TStates <= "100";
1112 Set_Addr_To <= aSP;
1113 LDW <= '1';
1114 Set_BusB_To <= "1101";
1115 when 4 =>
1116 Write <= '1';
1117 IncDec_16 <= "1111";
1118 Set_Addr_To <= aSP;
1119 Set_BusB_To <= "1100";
1120 when 5 =>
1121 Write <= '1';
1122 Call <= '1';
1123 when others => null;
1124 end case;
1125 when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
1126 if IR(5) = '0' or Mode /= 3 then
1127 -- CALL cc,nn
1128 MCycles <= "101";
1129 case to_integer(unsigned(MCycle)) is
1130 when 2 =>
1131 Inc_PC <= '1';
1132 LDZ <= '1';
1133 when 3 =>
1134 Inc_PC <= '1';
1135 LDW <= '1';
1136 if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
1137 IncDec_16 <= "1111";
1138 Set_Addr_TO <= aSP;
1139 TStates <= "100";
1140 Set_BusB_To <= "1101";
1141 else
1142 MCycles <= "011";
1143 end if;
1144 when 4 =>
1145 Write <= '1';
1146 IncDec_16 <= "1111";
1147 Set_Addr_To <= aSP;
1148 Set_BusB_To <= "1100";
1149 when 5 =>
1150 Write <= '1';
1151 Call <= '1';
1152 when others => null;
1153 end case;
1154 end if;
1155 when "11001001" =>
1156 -- RET
1157 MCycles <= "011";
1158 case to_integer(unsigned(MCycle)) is
1159 when 1 =>
1160 TStates <= "101";
1161 Set_Addr_TO <= aSP;
1162 when 2 =>
1163 IncDec_16 <= "0111";
1164 Set_Addr_To <= aSP;
1165 LDZ <= '1';
1166 when 3 =>
1167 Jump <= '1';
1168 IncDec_16 <= "0111";
1169 when others => null;
1170 end case;
1171 when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
1172 if IR(5) = '1' and Mode = 3 then
1173 case IRB(4 downto 3) is
1174 when "00" =>
1175 -- LD ($FF00+nn),A
1176 MCycles <= "011";
1177 case to_integer(unsigned(MCycle)) is
1178 when 2 =>
1179 Inc_PC <= '1';
1180 Set_Addr_To <= aIOA;
1181 Set_BusB_To <= "0111";
1182 when 3 =>
1183 Write <= '1';
1184 when others => null;
1185 end case;
1186 when "01" =>
1187 -- ADD SP,n
1188 MCycles <= "011";
1189 case to_integer(unsigned(MCycle)) is
1190 when 2 =>
1191 ALU_Op <= "0000";
1192 Inc_PC <= '1';
1193 Read_To_Reg <= '1';
1194 Save_ALU <= '1';
1195 Set_BusA_To <= "1000";
1196 Set_BusB_To <= "0110";
1197 when 3 =>
1198 NoRead <= '1';
1199 Read_To_Reg <= '1';
1200 Save_ALU <= '1';
1201 ALU_Op <= "0001";
1202 Set_BusA_To <= "1001";
1203 Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
1204 when others =>
1205 end case;
1206 when "10" =>
1207 -- LD A,($FF00+nn)
1208 MCycles <= "011";
1209 case to_integer(unsigned(MCycle)) is
1210 when 2 =>
1211 Inc_PC <= '1';
1212 Set_Addr_To <= aIOA;
1213 when 3 =>
1214 Read_To_Acc <= '1';
1215 when others => null;
1216 end case;
1217 when "11" =>
1218 -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!!
1219 MCycles <= "101";
1220 case to_integer(unsigned(MCycle)) is
1221 when 2 =>
1222 Inc_PC <= '1';
1223 LDZ <= '1';
1224 when 3 =>
1225 Set_Addr_To <= aZI;
1226 Inc_PC <= '1';
1227 LDW <= '1';
1228 when 4 =>
1229 Set_BusA_To(2 downto 0) <= "101"; -- L
1230 Read_To_Reg <= '1';
1231 Inc_WZ <= '1';
1232 Set_Addr_To <= aZI;
1233 when 5 =>
1234 Set_BusA_To(2 downto 0) <= "100"; -- H
1235 Read_To_Reg <= '1';
1236 when others => null;
1237 end case;
1238 end case;
1239 else
1240 -- RET cc
1241 MCycles <= "011";
1242 case to_integer(unsigned(MCycle)) is
1243 when 1 =>
1244 if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
1245 Set_Addr_TO <= aSP;
1246 else
1247 MCycles <= "001";
1248 end if;
1249 TStates <= "101";
1250 when 2 =>
1251 IncDec_16 <= "0111";
1252 Set_Addr_To <= aSP;
1253 LDZ <= '1';
1254 when 3 =>
1255 Jump <= '1';
1256 IncDec_16 <= "0111";
1257 when others => null;
1258 end case;
1259 end if;
1260 when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
1261 -- RST p
1262 MCycles <= "011";
1263 case to_integer(unsigned(MCycle)) is
1264 when 1 =>
1265 TStates <= "101";
1266 IncDec_16 <= "1111";
1267 Set_Addr_To <= aSP;
1268 Set_BusB_To <= "1101";
1269 when 2 =>
1270 Write <= '1';
1271 IncDec_16 <= "1111";
1272 Set_Addr_To <= aSP;
1273 Set_BusB_To <= "1100";
1274 when 3 =>
1275 Write <= '1';
1276 RstP <= '1';
1277 when others => null;
1278 end case;
1279
1280 -- INPUT AND OUTPUT GROUP
1281 when "11011011" =>
1282 if Mode /= 3 then
1283 -- IN A,(n)
1284 MCycles <= "011";
1285 case to_integer(unsigned(MCycle)) is
1286 when 2 =>
1287 Inc_PC <= '1';
1288 Set_Addr_To <= aIOA;
1289 when 3 =>
1290 Read_To_Acc <= '1';
1291 IORQ <= '1';
1292 when others => null;
1293 end case;
1294 end if;
1295 when "11010011" =>
1296 if Mode /= 3 then
1297 -- OUT (n),A
1298 MCycles <= "011";
1299 case to_integer(unsigned(MCycle)) is
1300 when 2 =>
1301 Inc_PC <= '1';
1302 Set_Addr_To <= aIOA;
1303 Set_BusB_To <= "0111";
1304 when 3 =>
1305 Write <= '1';
1306 IORQ <= '1';
1307 when others => null;
1308 end case;
1309 end if;
1310
1311 ------------------------------------------------------------------------------
1312 ------------------------------------------------------------------------------
1313 -- MULTIBYTE INSTRUCTIONS
1314 ------------------------------------------------------------------------------
1315 ------------------------------------------------------------------------------
1316
1317 when "11001011" =>
1318 if Mode /= 2 then
1319 Prefix <= "01";
1320 end if;
1321
1322 when "11101101" =>
1323 if Mode < 2 then
1324 Prefix <= "10";
1325 end if;
1326
1327 when "11011101"|"11111101" =>
1328 if Mode < 2 then
1329 Prefix <= "11";
1330 end if;
1331
1332 end case;
1333
1334 when "01" =>
1335
1336 ------------------------------------------------------------------------------
1337 --
1338 -- CB prefixed instructions
1339 --
1340 ------------------------------------------------------------------------------
1341
1342 Set_BusA_To(2 downto 0) <= IR(2 downto 0);
1343 Set_BusB_To(2 downto 0) <= IR(2 downto 0);
1344
1345 case IRB is
1346 when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
1347 |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
1348 |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
1349 |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
1350 |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
1351 |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
1352 |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
1353 |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
1354 -- RLC r
1355 -- RL r
1356 -- RRC r
1357 -- RR r
1358 -- SLA r
1359 -- SRA r
1360 -- SRL r
1361 -- SLL r (Undocumented) / SWAP r
1362 if MCycle = "001" then
1363 ALU_Op <= "1000";
1364 Read_To_Reg <= '1';
1365 Save_ALU <= '1';
1366 end if;
1367 when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
1368 -- RLC (HL)
1369 -- RL (HL)
1370 -- RRC (HL)
1371 -- RR (HL)
1372 -- SRA (HL)
1373 -- SRL (HL)
1374 -- SLA (HL)
1375 -- SLL (HL) (Undocumented) / SWAP (HL)
1376 MCycles <= "011";
1377 case to_integer(unsigned(MCycle)) is
1378 when 1 | 7 =>
1379 Set_Addr_To <= aXY;
1380 when 2 =>
1381 ALU_Op <= "1000";
1382 Read_To_Reg <= '1';
1383 Save_ALU <= '1';
1384 Set_Addr_To <= aXY;
1385 TStates <= "100";
1386 when 3 =>
1387 Write <= '1';
1388 when others =>
1389 end case;
1390 when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
1391 |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
1392 |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
1393 |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
1394 |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
1395 |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
1396 |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
1397 |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
1398 -- BIT b,r
1399 if MCycle = "001" then
1400 Set_BusB_To(2 downto 0) <= IR(2 downto 0);
1401 ALU_Op <= "1001";
1402 end if;
1403 when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
1404 -- BIT b,(HL)
1405 MCycles <= "010";
1406 case to_integer(unsigned(MCycle)) is
1407 when 1 | 7 =>
1408 Set_Addr_To <= aXY;
1409 when 2 =>
1410 ALU_Op <= "1001";
1411 TStates <= "100";
1412 when others =>
1413 end case;
1414 when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
1415 |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
1416 |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
1417 |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
1418 |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
1419 |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
1420 |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
1421 |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
1422 -- SET b,r
1423 if MCycle = "001" then
1424 ALU_Op <= "1010";
1425 Read_To_Reg <= '1';
1426 Save_ALU <= '1';
1427 end if;
1428 when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
1429 -- SET b,(HL)
1430 MCycles <= "011";
1431 case to_integer(unsigned(MCycle)) is
1432 when 1 | 7 =>
1433 Set_Addr_To <= aXY;
1434 when 2 =>
1435 ALU_Op <= "1010";
1436 Read_To_Reg <= '1';
1437 Save_ALU <= '1';
1438 Set_Addr_To <= aXY;
1439 TStates <= "100";
1440 when 3 =>
1441 Write <= '1';
1442 when others =>
1443 end case;
1444 when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
1445 |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
1446 |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
1447 |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
1448 |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
1449 |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
1450 |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
1451 |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
1452 -- RES b,r
1453 if MCycle = "001" then
1454 ALU_Op <= "1011";
1455 Read_To_Reg <= '1';
1456 Save_ALU <= '1';
1457 end if;
1458 when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
1459 -- RES b,(HL)
1460 MCycles <= "011";
1461 case to_integer(unsigned(MCycle)) is
1462 when 1 | 7 =>
1463 Set_Addr_To <= aXY;
1464 when 2 =>
1465 ALU_Op <= "1011";
1466 Read_To_Reg <= '1';
1467 Save_ALU <= '1';
1468 Set_Addr_To <= aXY;
1469 TStates <= "100";
1470 when 3 =>
1471 Write <= '1';
1472 when others =>
1473 end case;
1474 end case;
1475
1476 when others =>
1477
1478 ------------------------------------------------------------------------------
1479 --
1480 -- ED prefixed instructions
1481 --
1482 ------------------------------------------------------------------------------
1483
1484 case IRB is
1485 when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
1486 |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
1487 |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
1488 |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
1489 |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
1490 |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
1491 |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
1492 |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
1493
1494
1495 |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
1496 |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
1497 |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
1498 |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
1499 | "10100100"|"10100101"|"10100110"|"10100111"
1500 | "10101100"|"10101101"|"10101110"|"10101111"
1501 | "10110100"|"10110101"|"10110110"|"10110111"
1502 | "10111100"|"10111101"|"10111110"|"10111111"
1503 |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
1504 |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
1505 |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
1506 |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
1507 |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
1508 |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
1509 |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
1510 |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
1511 null; -- NOP, undocumented
1512 when "01111110"|"01111111" =>
1513 -- NOP, undocumented
1514 null;
1515 -- 8 BIT LOAD GROUP
1516 when "01010111" =>
1517 -- LD A,I
1518 Special_LD <= "100";
1519 TStates <= "101";
1520 when "01011111" =>
1521 -- LD A,R
1522 Special_LD <= "101";
1523 TStates <= "101";
1524 when "01000111" =>
1525 -- LD I,A
1526 Special_LD <= "110";
1527 TStates <= "101";
1528 when "01001111" =>
1529 -- LD R,A
1530 Special_LD <= "111";
1531 TStates <= "101";
1532 -- 16 BIT LOAD GROUP
1533 when "01001011"|"01011011"|"01101011"|"01111011" =>
1534 -- LD dd,(nn)
1535 MCycles <= "101";
1536 case to_integer(unsigned(MCycle)) is
1537 when 2 =>
1538 Inc_PC <= '1';
1539 LDZ <= '1';
1540 when 3 =>
1541 Set_Addr_To <= aZI;
1542 Inc_PC <= '1';
1543 LDW <= '1';
1544 when 4 =>
1545 Read_To_Reg <= '1';
1546 if IR(5 downto 4) = "11" then
1547 Set_BusA_To <= "1000";
1548 else
1549 Set_BusA_To(2 downto 1) <= IR(5 downto 4);
1550 Set_BusA_To(0) <= '1';
1551 end if;
1552 Inc_WZ <= '1';
1553 Set_Addr_To <= aZI;
1554 when 5 =>
1555 Read_To_Reg <= '1';
1556 if IR(5 downto 4) = "11" then
1557 Set_BusA_To <= "1001";
1558 else
1559 Set_BusA_To(2 downto 1) <= IR(5 downto 4);
1560 Set_BusA_To(0) <= '0';
1561 end if;
1562 when others => null;
1563 end case;
1564 when "01000011"|"01010011"|"01100011"|"01110011" =>
1565 -- LD (nn),dd
1566 MCycles <= "101";
1567 case to_integer(unsigned(MCycle)) is
1568 when 2 =>
1569 Inc_PC <= '1';
1570 LDZ <= '1';
1571 when 3 =>
1572 Set_Addr_To <= aZI;
1573 Inc_PC <= '1';
1574 LDW <= '1';
1575 if IR(5 downto 4) = "11" then
1576 Set_BusB_To <= "1000";
1577 else
1578 Set_BusB_To(2 downto 1) <= IR(5 downto 4);
1579 Set_BusB_To(0) <= '1';
1580 Set_BusB_To(3) <= '0';
1581 end if;
1582 when 4 =>
1583 Inc_WZ <= '1';
1584 Set_Addr_To <= aZI;
1585 Write <= '1';
1586 if IR(5 downto 4) = "11" then
1587 Set_BusB_To <= "1001";
1588 else
1589 Set_BusB_To(2 downto 1) <= IR(5 downto 4);
1590 Set_BusB_To(0) <= '0';
1591 Set_BusB_To(3) <= '0';
1592 end if;
1593 when 5 =>
1594 Write <= '1';
1595 when others => null;
1596 end case;
1597 when "10100000" | "10101000" | "10110000" | "10111000" =>
1598 -- LDI, LDD, LDIR, LDDR
1599 MCycles <= "100";
1600 case to_integer(unsigned(MCycle)) is
1601 when 1 =>
1602 Set_Addr_To <= aXY;
1603 IncDec_16 <= "1100"; -- BC
1604 when 2 =>
1605 Set_BusB_To <= "0110";
1606 Set_BusA_To(2 downto 0) <= "111";
1607 ALU_Op <= "0000";
1608 Set_Addr_To <= aDE;
1609 if IR(3) = '0' then
1610 IncDec_16 <= "0110"; -- IX
1611 else
1612 IncDec_16 <= "1110";
1613 end if;
1614 when 3 =>
1615 I_BT <= '1';
1616 TStates <= "101";
1617 Write <= '1';
1618 if IR(3) = '0' then
1619 IncDec_16 <= "0101"; -- DE
1620 else
1621 IncDec_16 <= "1101";
1622 end if;
1623 when 4 =>
1624 NoRead <= '1';
1625 TStates <= "101";
1626 when others => null;
1627 end case;
1628 when "10100001" | "10101001" | "10110001" | "10111001" =>
1629 -- CPI, CPD, CPIR, CPDR
1630 MCycles <= "100";
1631 case to_integer(unsigned(MCycle)) is
1632 when 1 =>
1633 Set_Addr_To <= aXY;
1634 IncDec_16 <= "1100"; -- BC
1635 when 2 =>
1636 Set_BusB_To <= "0110";
1637 Set_BusA_To(2 downto 0) <= "111";
1638 ALU_Op <= "0111";
1639 Save_ALU <= '1';
1640 PreserveC <= '1';
1641 if IR(3) = '0' then
1642 IncDec_16 <= "0110";
1643 else
1644 IncDec_16 <= "1110";
1645 end if;
1646 when 3 =>
1647 NoRead <= '1';
1648 I_BC <= '1';
1649 TStates <= "101";
1650 when 4 =>
1651 NoRead <= '1';
1652 TStates <= "101";
1653 when others => null;
1654 end case;
1655 when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
1656 -- NEG
1657 Alu_OP <= "0010";
1658 Set_BusB_To <= "0111";
1659 Set_BusA_To <= "1010";
1660 Read_To_Acc <= '1';
1661 Save_ALU <= '1';
1662 when "01000110"|"01001110"|"01100110"|"01101110" =>
1663 -- IM 0
1664 IMode <= "00";
1665 when "01010110"|"01110110" =>
1666 -- IM 1
1667 IMode <= "01";
1668 when "01011110"|"01110111" =>
1669 -- IM 2
1670 IMode <= "10";
1671 -- 16 bit arithmetic
1672 when "01001010"|"01011010"|"01101010"|"01111010" =>
1673 -- ADC HL,ss
1674 MCycles <= "011";
1675 case to_integer(unsigned(MCycle)) is
1676 when 2 =>
1677 NoRead <= '1';
1678 ALU_Op <= "0001";
1679 Read_To_Reg <= '1';
1680 Save_ALU <= '1';
1681 Set_BusA_To(2 downto 0) <= "101";
1682 case to_integer(unsigned(IR(5 downto 4))) is
1683 when 0|1|2 =>
1684 Set_BusB_To(2 downto 1) <= IR(5 downto 4);
1685 Set_BusB_To(0) <= '1';
1686 when others =>
1687 Set_BusB_To <= "1000";
1688 end case;
1689 TStates <= "100";
1690 when 3 =>
1691 NoRead <= '1';
1692 Read_To_Reg <= '1';
1693 Save_ALU <= '1';
1694 ALU_Op <= "0001";
1695 Set_BusA_To(2 downto 0) <= "100";
1696 case to_integer(unsigned(IR(5 downto 4))) is
1697 when 0|1|2 =>
1698 Set_BusB_To(2 downto 1) <= IR(5 downto 4);
1699 Set_BusB_To(0) <= '0';
1700 when others =>
1701 Set_BusB_To <= "1001";
1702 end case;
1703 when others =>
1704 end case;
1705 when "01000010"|"01010010"|"01100010"|"01110010" =>
1706 -- SBC HL,ss
1707 MCycles <= "011";
1708 case to_integer(unsigned(MCycle)) is
1709 when 2 =>
1710 NoRead <= '1';
1711 ALU_Op <= "0011";
1712 Read_To_Reg <= '1';
1713 Save_ALU <= '1';
1714 Set_BusA_To(2 downto 0) <= "101";
1715 case to_integer(unsigned(IR(5 downto 4))) is
1716 when 0|1|2 =>
1717 Set_BusB_To(2 downto 1) <= IR(5 downto 4);
1718 Set_BusB_To(0) <= '1';
1719 when others =>
1720 Set_BusB_To <= "1000";
1721 end case;
1722 TStates <= "100";
1723 when 3 =>
1724 NoRead <= '1';
1725 ALU_Op <= "0011";
1726 Read_To_Reg <= '1';
1727 Save_ALU <= '1';
1728 Set_BusA_To(2 downto 0) <= "100";
1729 case to_integer(unsigned(IR(5 downto 4))) is
1730 when 0|1|2 =>
1731 Set_BusB_To(2 downto 1) <= IR(5 downto 4);
1732 when others =>
1733 Set_BusB_To <= "1001";
1734 end case;
1735 when others =>
1736 end case;
1737 when "01101111" =>
1738 -- RLD
1739 MCycles <= "100";
1740 case to_integer(unsigned(MCycle)) is
1741 when 2 =>
1742 NoRead <= '1';
1743 Set_Addr_To <= aXY;
1744 when 3 =>
1745 Read_To_Reg <= '1';
1746 Set_BusB_To(2 downto 0) <= "110";
1747 Set_BusA_To(2 downto 0) <= "111";
1748 ALU_Op <= "1101";
1749 TStates <= "100";
1750 Set_Addr_To <= aXY;
1751 Save_ALU <= '1';
1752 when 4 =>
1753 I_RLD <= '1';
1754 Write <= '1';
1755 when others =>
1756 end case;
1757 when "01100111" =>
1758 -- RRD
1759 MCycles <= "100";
1760 case to_integer(unsigned(MCycle)) is
1761 when 2 =>
1762 Set_Addr_To <= aXY;
1763 when 3 =>
1764 Read_To_Reg <= '1';
1765 Set_BusB_To(2 downto 0) <= "110";
1766 Set_BusA_To(2 downto 0) <= "111";
1767 ALU_Op <= "1110";
1768 TStates <= "100";
1769 Set_Addr_To <= aXY;
1770 Save_ALU <= '1';
1771 when 4 =>
1772 I_RRD <= '1';
1773 Write <= '1';
1774 when others =>
1775 end case;
1776 when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
1777 -- RETI, RETN
1778 MCycles <= "011";
1779 case to_integer(unsigned(MCycle)) is
1780 when 1 =>
1781 Set_Addr_TO <= aSP;
1782 when 2 =>
1783 IncDec_16 <= "0111";
1784 Set_Addr_To <= aSP;
1785 LDZ <= '1';
1786 when 3 =>
1787 Jump <= '1';
1788 IncDec_16 <= "0111";
1789 I_RETN <= '1';
1790 when others => null;
1791 end case;
1792 when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
1793 -- IN r,(C)
1794 MCycles <= "010";
1795 case to_integer(unsigned(MCycle)) is
1796 when 1 =>
1797 Set_Addr_To <= aBC;
1798 when 2 =>
1799 IORQ <= '1';
1800 if IR(5 downto 3) /= "110" then
1801 Read_To_Reg <= '1';
1802 Set_BusA_To(2 downto 0) <= IR(5 downto 3);
1803 end if;
1804 I_INRC <= '1';
1805 when others =>
1806 end case;
1807 when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
1808 -- OUT (C),r
1809 -- OUT (C),0
1810 MCycles <= "010";
1811 case to_integer(unsigned(MCycle)) is
1812 when 1 =>
1813 Set_Addr_To <= aBC;
1814 Set_BusB_To(2 downto 0) <= IR(5 downto 3);
1815 if IR(5 downto 3) = "110" then
1816 Set_BusB_To(3) <= '1';
1817 end if;
1818 when 2 =>
1819 Write <= '1';
1820 IORQ <= '1';
1821 when others =>
1822 end case;
1823 when "10100010" | "10101010" | "10110010" | "10111010" =>
1824 -- INI, IND, INIR, INDR
1825 MCycles <= "100";
1826 case to_integer(unsigned(MCycle)) is
1827 when 1 =>
1828 Set_Addr_To <= aBC;
1829 Set_BusB_To <= "1010";
1830 Set_BusA_To <= "0000";
1831 Read_To_Reg <= '1';
1832 Save_ALU <= '1';
1833 ALU_Op <= "0010";
1834 when 2 =>
1835 IORQ <= '1';
1836 Set_BusB_To <= "0110";
1837 Set_Addr_To <= aXY;
1838 when 3 =>
1839 if IR(3) = '0' then
1840 IncDec_16 <= "0010";
1841 else
1842 IncDec_16 <= "1010";
1843 end if;
1844 TStates <= "100";
1845 Write <= '1';
1846 I_BTR <= '1';
1847 when 4 =>
1848 NoRead <= '1';
1849 TStates <= "101";
1850 when others => null;
1851 end case;
1852 when "10100011" | "10101011" | "10110011" | "10111011" =>
1853 -- OUTI, OUTD, OTIR, OTDR
1854 MCycles <= "100";
1855 case to_integer(unsigned(MCycle)) is
1856 when 1 =>
1857 TStates <= "101";
1858 Set_Addr_To <= aXY;
1859 Set_BusB_To <= "1010";
1860 Set_BusA_To <= "0000";
1861 Read_To_Reg <= '1';
1862 Save_ALU <= '1';
1863 ALU_Op <= "0010";
1864 when 2 =>
1865 Set_BusB_To <= "0110";
1866 Set_Addr_To <= aBC;
1867 when 3 =>
1868 if IR(3) = '0' then
1869 IncDec_16 <= "0010";
1870 else
1871 IncDec_16 <= "1010";
1872 end if;
1873 IORQ <= '1';
1874 Write <= '1';
1875 I_BTR <= '1';
1876 when 4 =>
1877 NoRead <= '1';
1878 TStates <= "101";
1879 when others => null;
1880 end case;
1881 end case;
1882
1883 end case;
1884
1885 if Mode = 1 then
1886 if MCycle = "001" then
1887 -- TStates <= "100";
1888 else
1889 TStates <= "011";
1890 end if;
1891 end if;
1892
1893 if Mode = 3 then
1894 if MCycle = "001" then
1895 -- TStates <= "100";
1896 else
1897 TStates <= "100";
1898 end if;
1899 end if;
1900
1901 if Mode < 2 then
1902 if MCycle = "110" then
1903 Inc_PC <= '1';
1904 if Mode = 1 then
1905 Set_Addr_To <= aXY;
1906 TStates <= "100";
1907 Set_BusB_To(2 downto 0) <= SSS;
1908 Set_BusB_To(3) <= '0';
1909 end if;
1910 if IRB = "00110110" or IRB = "11001011" then
1911 Set_Addr_To <= aNone;
1912 end if;
1913 end if;
1914 if MCycle = "111" then
1915 if Mode = 0 then
1916 TStates <= "101";
1917 end if;
1918 if ISet /= "01" then
1919 Set_Addr_To <= aXY;
1920 end if;
1921 Set_BusB_To(2 downto 0) <= SSS;
1922 Set_BusB_To(3) <= '0';
1923 if IRB = "00110110" or ISet = "01" then
1924 -- LD (HL),n
1925 Inc_PC <= '1';
1926 else
1927 NoRead <= '1';
1928 end if;
1929 end if;
1930 end if;
1931
1932 end process;
1933
1934 end;
Arcade Games for FPGAs (currently only galaxian)
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