65525ba1e207f48c7b5a5da12be72cf7715446d1
[fpga-games] / galaxian / src / mc_adec.v
1 //---------------------------------------------------------------------
2 // FPGA GALAXIAN ADDRESS DECDER
3 //
4 // Version : 2.01
5 //
6 // Copyright(c) 2004 Katsumi Degawa , All rights reserved
7 //
8 // Important !
9 //
10 // This program is freeware for non-commercial use.
11 // An author does no guarantee about this program.
12 // You can use this under your own risk.
13 //
14 // 2004- 4-30 galaxian modify by K.DEGAWA
15 // 2004- 5- 6 first release.
16 // 2004- 8-23 Improvement with T80-IP.
17 //---------------------------------------------------------------------
18 //
19 //GALAXIAN Address Map
20 //
21 // Address Item(R..read-mode W..wight-mode) Parts
22 //0000 - 1FFF CPU-ROM..R ( 7H or 7K )
23 //2000 - 3FFF CPU-ROM..R ( 7L )
24 //4000 - 47FF CPU-RAM..RW ( 7N & 7P )
25 //5000 - 57FF VID-RAM..RW
26 //5800 - 5FFF OBJ-RAM..RW
27 //6000 - SW0..R LAMP......W
28 //6800 - SW1..R SOUND.....W
29 //7000 - DIP..R
30 //7001 NMI_ON....W
31 //7004 STARS_ON..W
32 //7006 H_FLIP....W
33 //7007 V-FLIP....W
34 //7800 WDR..R PITCH.....W
35 //
36 //W MODE
37 //6000 - 6002
38 //6003 COIN CNTR
39 //6004 - 6007 SOUND CONTROL(OSC)
40 //
41 //6800 SOUND CONTROL(FS1)
42 //6801 SOUND CONTROL(FS2)
43 //6802 SOUND CONTROL(FS3)
44 //6803 SOUND CONTROL(HIT)
45 //6805 SOUND CONTROL(SHOT)
46 //6806 SOUND CONTROL(VOL1)
47 //6807 SOUND CONTROL(VOL2)
48 //
49
50 module mc_adec(
51
52 I_CLK_12M,
53 I_CLK_6M,
54 I_CPU_CLK,
55 I_RSTn,
56
57 I_CPU_A,
58 I_CPU_D,
59 I_MREQn,
60 I_RFSHn,
61 I_RDn,
62 I_WRn,
63 I_H_BL,
64 I_V_BLn,
65
66 O_WAITn,
67 O_NMIn,
68 O_CPU_ROM_CSn,
69 O_CPU_RAM_RDn,
70 O_CPU_RAM_WRn,
71 O_CPU_RAM_CSn,
72 O_OBJ_RAM_RDn,
73 O_OBJ_RAM_WRn,
74 O_OBJ_RAM_RQn,
75 O_VID_RAM_RDn,
76 O_VID_RAM_WRn,
77 O_SW0_OEn,
78 O_SW1_OEn,
79 O_DIP_OEn,
80 O_WDR_OEn,
81 O_LAMP_WEn,
82 O_SOUND_WEn,
83 O_PITCHn,
84 O_H_FLIP,
85 O_V_FLIP,
86 O_BD_G,
87 O_STARS_ON
88
89 );
90
91
92 input I_CLK_12M;
93 input I_CLK_6M;
94 input I_CPU_CLK;
95 input I_RSTn;
96
97 input [15:0]I_CPU_A;
98 input I_CPU_D;
99 input I_MREQn;
100 input I_RFSHn;
101 input I_RDn;
102 input I_WRn;
103 input I_H_BL;
104 input I_V_BLn;
105
106 output O_WAITn;
107 output O_NMIn;
108 output O_CPU_ROM_CSn;
109 output O_CPU_RAM_RDn;
110 output O_CPU_RAM_WRn;
111 output O_CPU_RAM_CSn;
112 output O_OBJ_RAM_RDn;
113 output O_OBJ_RAM_WRn;
114 output O_OBJ_RAM_RQn;
115 output O_VID_RAM_RDn;
116 output O_VID_RAM_WRn;
117 output O_SW0_OEn;
118 output O_SW1_OEn;
119 output O_DIP_OEn;
120 output O_WDR_OEn;
121 output O_LAMP_WEn;
122 output O_SOUND_WEn;
123 output O_PITCHn;
124 output O_H_FLIP;
125 output O_V_FLIP;
126 output O_BD_G;
127 output O_STARS_ON;
128
129
130 wire [3:0]W_8E1_Q;
131 wire [3:0]W_8E2_Q;
132 wire [7:0]W_8P_Q,W_8N_Q,W_8M_Q;
133 reg [7:0]W_9N_Q;
134 wire W_NMI_ONn = W_9N_Q[1]; // galaxian
135 //------ CPU WAITn ----------------------------------------------
136
137 reg W_6S1_Q,W_6S1_Qn;
138 reg W_6S2_Qn;
139
140 //assign O_WAITn = W_6S1_Qn;
141 assign O_WAITn = 1'b1 ; // No Wait
142
143 always@(posedge I_CPU_CLK or negedge I_V_BLn)
144 begin
145 if(I_V_BLn == 1'b0)begin
146 W_6S1_Q <= 1'b0;
147 W_6S1_Qn <= 1'b1;
148 end
149 else begin
150 W_6S1_Q <= ~(I_H_BL | W_8P_Q[2]);
151 W_6S1_Qn <= I_H_BL | W_8P_Q[2];
152 end
153 end
154
155 always@(negedge I_CPU_CLK)
156 begin
157 W_6S2_Qn <= ~W_6S1_Q;
158 end
159 //------ CPU NMIn -----------------------------------------------
160 wire W_V_BL = ~I_V_BLn;
161 reg O_NMIn;
162 always@(posedge W_V_BL or negedge W_NMI_ONn)
163 begin
164 if(~W_NMI_ONn)
165 O_NMIn <= 1'b1;
166 else
167 O_NMIn <= 1'b0;
168 end
169 //-----------------------------------------------------------------
170 logic_74xx139 U_8E1(
171
172 .I_G(I_MREQn),
173 .I_Sel(I_CPU_A[15:14]),
174 .O_Q(W_8E1_Q)
175
176 );
177
178 //-------- CPU_ROM CS 0000 - 3FFF ---------------------------
179 logic_74xx139 U_8E2(
180
181 .I_G(I_RDn),
182 .I_Sel({W_8E1_Q[0],I_CPU_A[13]}),
183 .O_Q(W_8E2_Q)
184
185 );
186
187 assign O_CPU_ROM_CSn = W_8E2_Q[0]&W_8E2_Q[1] ; // 0000 - 3FFF
188 //-----------------------------------------------------------------
189 // ADDRESS
190 // W_8E1_Q[0] = 0000 - 3FFF ---- CPU_ROM_USE
191 // W_8E1_Q[1] = 4000 - 7FFF ---- GALAXIAN USE *1
192 // W_8E1_Q[2] = 8000 - BFFF ---- MOONCREST USE
193 // W_8E1_Q[3] = C000 - FFFF
194
195 logic_74xx138 U_8P(
196
197 .I_G1(I_RFSHn),
198 .I_G2a(W_8E1_Q[1]), // <= *1
199 .I_G2b(W_8E1_Q[1]), // <= *1
200 .I_Sel(I_CPU_A[13:11]),
201 .O_Q(W_8P_Q)
202
203 );
204
205 logic_74xx138 U_8N(
206
207 .I_G1(1'b1),
208 .I_G2a(I_RDn),
209 .I_G2b(W_8E1_Q[1]), // <= *1
210 .I_Sel(I_CPU_A[13:11]),
211 .O_Q(W_8N_Q)
212
213 );
214
215 logic_74xx138 U_8M(
216
217 //.I_G1(W_6S2_Qn),
218 .I_G1(1'b1), // No Wait
219 .I_G2a(I_WRn),
220 .I_G2b(W_8E1_Q[1]), // <= *1
221 .I_Sel(I_CPU_A[13:11]),
222 .O_Q(W_8M_Q)
223
224 );
225
226 assign O_BD_G = ~(W_8E1_Q[0]&W_8P_Q[0]); //
227 assign O_OBJ_RAM_RQn = W_8P_Q[3]; //
228
229 assign O_CPU_RAM_CSn = W_8N_Q[0]&W_8M_Q[0]; //
230 assign O_CPU_RAM_RDn = W_8N_Q[0]; //
231 assign O_CPU_RAM_WRn = W_8M_Q[0]; //
232 assign O_VID_RAM_RDn = W_8N_Q[2]; //
233 assign O_OBJ_RAM_RDn = W_8N_Q[3]; //
234 assign O_SW0_OEn = W_8N_Q[4]; //
235 assign O_SW1_OEn = W_8N_Q[5]; //
236 assign O_DIP_OEn = W_8N_Q[6]; //
237 assign O_WDR_OEn = W_8N_Q[7]; //
238
239 assign O_VID_RAM_WRn = W_8M_Q[2]; //
240 assign O_OBJ_RAM_WRn = W_8M_Q[3]; //
241 assign O_LAMP_WEn = W_8M_Q[4]; //
242 assign O_SOUND_WEn = W_8M_Q[5]; //
243
244 assign O_PITCHn = W_8M_Q[7]; //
245
246 //--- Parts 9N ---------
247
248 always@(posedge I_CLK_12M or negedge I_RSTn)
249 begin
250 if(I_RSTn == 1'b0)begin
251 W_9N_Q <= 0;
252 end
253 else begin
254 if(W_8M_Q[6] == 1'b0)begin
255 case(I_CPU_A[2:0])
256 3'h0 : W_9N_Q[0] <= I_CPU_D;
257 3'h1 : W_9N_Q[1] <= I_CPU_D;
258 3'h2 : W_9N_Q[2] <= I_CPU_D;
259 3'h3 : W_9N_Q[3] <= I_CPU_D;
260 3'h4 : W_9N_Q[4] <= I_CPU_D;
261 3'h5 : W_9N_Q[5] <= I_CPU_D;
262 3'h6 : W_9N_Q[6] <= I_CPU_D;
263 3'h7 : W_9N_Q[7] <= I_CPU_D;
264 endcase
265 end
266 end
267 end
268
269 assign O_STARS_ON = W_9N_Q[4]; //
270 assign O_H_FLIP = W_9N_Q[6]; //
271 assign O_V_FLIP = W_9N_Q[7]; //
272
273
274 endmodule
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