git.zerfleddert.de Git - fpga-games/blob - galaxian/t80_ip/T80_RegX.vhd

   1 -- ****
   2 -- T80(b) core. In an effort to merge and maintain bug fixes ....
   3 --
   4 --
   5 -- Ver 300 started tidyup
   6 -- MikeJ March 2005
   7 -- Latest version from www.fpgaarcade.com (original www.opencores.org)
   8 --
   9 -- ****
  10 --
  11 -- T80 Registers for Xilinx Select RAM
  12 --
  13 -- Version : 0244
  14 --
  15 -- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
  16 --
  17 -- All rights reserved
  18 --
  19 -- Redistribution and use in source and synthezised forms, with or without
  20 -- modification, are permitted provided that the following conditions are met:
  21 --
  22 -- Redistributions of source code must retain the above copyright notice,
  23 -- this list of conditions and the following disclaimer.
  24 --
  25 -- Redistributions in synthesized form must reproduce the above copyright
  26 -- notice, this list of conditions and the following disclaimer in the
  27 -- documentation and/or other materials provided with the distribution.
  28 --
  29 -- Neither the name of the author nor the names of other contributors may
  30 -- be used to endorse or promote products derived from this software without
  31 -- specific prior written permission.
  32 --
  33 -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  34 -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  35 -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  36 -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
  37 -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  38 -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  39 -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  40 -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  41 -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  42 -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  43 -- POSSIBILITY OF SUCH DAMAGE.
  44 --
  45 -- Please report bugs to the author, but before you do so, please
  46 -- make sure that this is not a derivative work and that
  47 -- you have the latest version of this file.
  48 --
  49 -- The latest version of this file can be found at:
  50 --      http://www.opencores.org/cvsweb.shtml/t51/
  51 --
  52 -- Limitations :
  53 --
  54 -- File history :
  55 --
  56 --      0242 : Initial release
  57 --
  58 --      0244 : Removed UNISIM library and added componet declaration
  59 --
  60
  61 library IEEE;
  62 use IEEE.std_logic_1164.all;
  63 use IEEE.numeric_std.all;
  64
  65 entity T80_Reg is
  66         port(
  67                 Clk                     : in std_logic;
  68                 CEN                     : in std_logic;
  69                 WEH                     : in std_logic;
  70                 WEL                     : in std_logic;
  71                 AddrA           : in std_logic_vector(2 downto 0);
  72                 AddrB           : in std_logic_vector(2 downto 0);
  73                 AddrC           : in std_logic_vector(2 downto 0);
  74                 DIH                     : in std_logic_vector(7 downto 0);
  75                 DIL                     : in std_logic_vector(7 downto 0);
  76                 DOAH            : out std_logic_vector(7 downto 0);
  77                 DOAL            : out std_logic_vector(7 downto 0);
  78                 DOBH            : out std_logic_vector(7 downto 0);
  79                 DOBL            : out std_logic_vector(7 downto 0);
  80                 DOCH            : out std_logic_vector(7 downto 0);
  81                 DOCL            : out std_logic_vector(7 downto 0)
  82         );
  83 end T80_Reg;
  84
  85 architecture rtl of T80_Reg is
  86
  87         component RAM16X1D
  88                 port(
  89                         DPO         : out std_ulogic;
  90                         SPO         : out std_ulogic;
  91                         A0          : in std_ulogic;
  92                         A1          : in std_ulogic;
  93                         A2          : in std_ulogic;
  94                         A3          : in std_ulogic;
  95                         D           : in std_ulogic;
  96                         DPRA0       : in std_ulogic;
  97                         DPRA1       : in std_ulogic;
  98                         DPRA2       : in std_ulogic;
  99                         DPRA3       : in std_ulogic;
 100                         WCLK        : in std_ulogic;
 101                         WE          : in std_ulogic);
 102         end component;
 103
 104         signal      ENH             : std_logic;
 105         signal      ENL             : std_logic;
 106
 107 begin
 108
 109         ENH <= CEN and WEH;
 110         ENL <= CEN and WEL;
 111
 112         bG1: for I in 0 to 7 generate
 113         begin
 114                 Reg1H : RAM16X1D
 115                         port map(
 116                         DPO => DOBH(i),
 117                         SPO => DOAH(i),
 118                         A0 => AddrA(0),
 119                         A1 => AddrA(1),
 120                         A2 => AddrA(2),
 121                         A3 => '0',
 122                         D => DIH(i),
 123                         DPRA0 => AddrB(0),
 124                         DPRA1 => AddrB(1),
 125                         DPRA2 => AddrB(2),
 126                         DPRA3 => '0',
 127                         WCLK => Clk,
 128                         WE => ENH);
 129                 Reg1L : RAM16X1D
 130                         port map(
 131                         DPO => DOBL(i),
 132                         SPO => DOAL(i),
 133                         A0 => AddrA(0),
 134                         A1 => AddrA(1),
 135                         A2 => AddrA(2),
 136                         A3 => '0',
 137                         D => DIL(i),
 138                         DPRA0 => AddrB(0),
 139                         DPRA1 => AddrB(1),
 140                         DPRA2 => AddrB(2),
 141                         DPRA3 => '0',
 142                         WCLK => Clk,
 143                         WE => ENL);
 144                 Reg2H : RAM16X1D
 145                         port map(
 146                         DPO => DOCH(i),
 147                         SPO => open,
 148                         A0 => AddrA(0),
 149                         A1 => AddrA(1),
 150                         A2 => AddrA(2),
 151                         A3 => '0',
 152                         D => DIH(i),
 153                         DPRA0 => AddrC(0),
 154                         DPRA1 => AddrC(1),
 155                         DPRA2 => AddrC(2),
 156                         DPRA3 => '0',
 157                         WCLK => Clk,
 158                         WE => ENH);
 159                 Reg2L : RAM16X1D
 160                         port map(
 161                         DPO => DOCL(i),
 162                         SPO => open,
 163                         A0 => AddrA(0),
 164                         A1 => AddrA(1),
 165                         A2 => AddrA(2),
 166                         A3 => '0',
 167                         D => DIL(i),
 168                         DPRA0 => AddrC(0),
 169                         DPRA1 => AddrC(1),
 170                         DPRA2 => AddrC(2),
 171                         DPRA3 => '0',
 172                         WCLK => Clk,
 173                         WE => ENL);
 174         end generate;
 175
 176 end;