match bit order of vga output to bit order of Spartan 3ADSP kit

[fpga-games] / galaxian / galaxian.ucf

diff --git a/galaxian/galaxian.ucf b/galaxian/galaxian.ucf
index 6fb6807e5c216fec23fde2cf01c4fa4b83406c5e..04fc6912f5a3dc61b80f1e359257bf6d5bd2fd62 100644 (file)
--- a/galaxian/galaxian.ucf
+++ b/galaxian/galaxian.ucf
@@ -1,5 +1,11 @@
-### UCF file for FPGA-MOONCRST on XC2S200E
-#
+CONFIG PART = XC3SD1800A-FG676-4;
+
+NET I_CLK_125M TNM_NET = clk_ref_grp;
+TIMESPEC TS01 = PERIOD : clk_ref_grp : 8.00 : PRIORITY 1; #125 MHz
+
+TIMESPEC TS11=FROM:PADS:TO:FFS : 30 ns;
+TIMESPEC TS12=FROM:FFS:TO:PADS : 30 ns;
+
 #---------- MasterClock 18.432MHz ----------
 NET "I_CLK_125M" LOC = "F13" | IOSTANDARD = LVCMOS33;
 #-------------------------------------------
@@ -51,21 +57,18 @@ NET "O_SOUND_OUT_L" LOC = "AA22" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8;
 NET "O_SOUND_OUT_R" LOC = "V19" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8;
 #-------------------------------------------
 #--------- VIDEO I/F -----------------------
-NET "O_VGA_R<0>" LOC = "V18" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
-NET "O_VGA_R<1>" LOC = "F24" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "O_VGA_R<0>" LOC = "L20" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "O_VGA_R<1>" LOC = "K20" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
 NET "O_VGA_R<2>" LOC = "F25" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
-NET "O_VGA_R<3>" LOC = "K20" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
-NET "O_VGA_R<4>" LOC = "L20" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
-NET "O_VGA_G<0>" LOC = "T17" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
-NET "O_VGA_G<1>" LOC = "J22" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "O_VGA_R<3>" LOC = "F24" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "O_VGA_G<0>" LOC = "M19" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "O_VGA_G<1>" LOC = "M18" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
 NET "O_VGA_G<2>" LOC = "J23" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
-NET "O_VGA_G<3>" LOC = "M18" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
-NET "O_VGA_G<4>" LOC = "M19" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
-NET "O_VGA_B<0>" LOC = "Y25" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
-NET "O_VGA_B<1>" LOC = "G24" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
-NET "O_VGA_B<2>" LOC = "G23"  | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
-NET "O_VGA_B<3>" LOC = "K21"  | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
-NET "O_VGA_B<4>" LOC = "L22"  | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "O_VGA_G<3>" LOC = "J22" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "O_VGA_B<0>" LOC = "L22" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "O_VGA_B<1>" LOC = "K21" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "O_VGA_B<2>" LOC = "G23" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "O_VGA_B<3>" LOC = "G24" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
 
 NET "O_VGA_H_SYNCn" LOC = "K26" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
 NET "O_VGA_V_SYNCn" LOC = "K25" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;