X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/fpga-games/blobdiff_plain/3f141b4135f7b5710b988f5fc204b24301240d2b..36a47d3c8d89db7f85847c9d0b8985a52a914409:/galaxian/src/mc_top.v

diff --git a/galaxian/src/mc_top.v b/galaxian/src/mc_top.v
index 08d25de..99a4a6a 100644
--- a/galaxian/src/mc_top.v
+++ b/galaxian/src/mc_top.v
@@ -33,13 +33,6 @@ psTXD,
 psRXD,
 `endif
 
-//    ROM IF
-//O_ROM_AB,
-//I_ROM_DB,
-//O_ROM_OEn,
-//O_ROM_CSn,
-//O_ROM_WEn,
-
 //    INPORT SW IF
 I_PSW,
 
@@ -80,13 +73,6 @@ input	psRXD;
 output	psTXD,psCLK,psSEL;
 `endif
 
-//    ROM IF
-//output [18:0]O_ROM_AB;
-//input  [7:0]I_ROM_DB;
-//output O_ROM_OEn;
-//output O_ROM_CSn;
-//output O_ROM_WEn;
-
 //    INPORT SW IF
 input  [8:0]I_PSW;
 
@@ -107,13 +93,11 @@ wire   I_CLK_18432M;
 wire   W_CLK_12M,WB_CLK_12M;
 wire   W_CLK_6M,WB_CLK_6M;
 wire   W_STARS_CLK;
-wire   W_ROM_CLK;
 
 mc_dcm clockgen(
 .CLKIN_IN(I_CLK_125M),
 .RST_IN(! W_RESETn),
-.CLKFX_OUT(I_CLK_18432M),
-.CLK0_OUT(W_ROM_CLK)
+.CLKFX_OUT(I_CLK_18432M)
 );
 
 //------ H&V COUNTER -------------------------
@@ -412,71 +396,23 @@ mc_inport MC_INPORT(
 //-----------------------------------------------------------------------------
 //------- ROM           -------------------------------------------------------
 reg    [18:0]ROM_A;
-wire   [10:0]W_OBJ_ROM_A;
-reg    [7:0]W_OBJ_ROM_A_D;
-reg    [7:0]W_OBJ_ROM_B_D;
 
 wire   [18:0]W_WAV_A0,W_WAV_A1,W_WAV_A2;
 reg    [7:0]W_WAV_D0,W_WAV_D1,W_WAV_D2;
 
-wire   [7:0]ROM_D; // = I_ROM_DB;
-//assign O_ROM_AB  = ROM_A;
-
-//assign O_ROM_OEn = 1'b0;
-//assign O_ROM_CSn = 1'b0;
-//assign O_ROM_WEn = 1'b1;
+wire   [7:0]ROM_D;
 
 galaxian_roms ROMS(
-.I_ROM_CLK(W_ROM_CLK),
-.I_ADDR(ROM_A),
+.I_ROM_CLK(W_CLK_12M),
+.I_ADDR({3'h0,W_A[15:0]}),
 .O_DATA(ROM_D)
 );
 
-
-reg    [1:0]clk_d;
-reg    [4:0]seq;
-always @(posedge I_CLK_18432M)
+always@(posedge W_CLK_12M)
 begin
-  // 24 phase generator
-   clk_d[0] <= W_H_CNT[0] & W_H_CNT[1] & W_H_CNT[2];
-   clk_d[1] <= clk_d[0];
-   seq <= (~clk_d[1] & clk_d[0]) ? 0 : seq+1;
-   case(seq)
-      0:begin
-        ROM_A <= W_WAV_A0;
-        W_CPU_ROM_DO <= ROM_D;
-        end
-      2:begin
-        ROM_A <= W_WAV_A1;
-        W_WAV_D0 <= ROM_D;
-        end
-      4:begin
-        ROM_A <= {3'h0,W_A[15:0]};
-        W_WAV_D1 <= ROM_D;
-        end
-      6:begin
-        ROM_A <= W_WAV_A2;
-        W_CPU_ROM_DO <= ROM_D;
-        end
-      8:W_WAV_D2 <= ROM_D;
-     10:ROM_A <= {3'h0,W_A[15:0]};
-     12:W_CPU_ROM_DO <= ROM_D;
-     14:ROM_A <= {3'h0,W_A[15:0]};
-     16:begin
-        ROM_A <= {3'h0,4'h4,1'b0,W_OBJ_ROM_A};
-        W_CPU_ROM_DO <= ROM_D;
-        end
-     18:begin
-        ROM_A <= {3'h0,4'h5,1'b0,W_OBJ_ROM_A};
-        W_OBJ_ROM_A_D <= ROM_D;
-        end
-     20:begin
-        ROM_A <= {3'h0,W_A[15:0]};
-        W_OBJ_ROM_B_D <= ROM_D;
-        end
-     default:;
-   endcase
+	W_CPU_ROM_DO <= ROM_D;
 end
+
 //-----------------------------------------------------------------------------
 
 wire   W_V_BL2n;
@@ -527,10 +463,6 @@ mc_video MC_VID(
 .I_VID_RAM_RDn(W_VID_RAM_RDn),
 .I_VID_RAM_WRn(W_VID_RAM_WRn),
 
-.O_OBJ_ROM_A(W_OBJ_ROM_A),
-.I_OBJ_ROM_A_D(W_OBJ_ROM_A_D),
-.I_OBJ_ROM_B_D(W_OBJ_ROM_B_D),
-
 .O_C_BLnX(W_C_BLnX),
 .O_8HF(W_8HF),
 .O_256HnX(W_256HnX),