X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/fpga-games/blobdiff_plain/3fc34adfa51bd78e346143103b498bf962ea1b46..36a47d3c8d89db7f85847c9d0b8985a52a914409:/galaxian/src/mc_top.v?ds=inline

diff --git a/galaxian/src/mc_top.v b/galaxian/src/mc_top.v
index a8d2ca8..99a4a6a 100644
--- a/galaxian/src/mc_top.v
+++ b/galaxian/src/mc_top.v
@@ -33,13 +33,6 @@ psTXD,
 psRXD,
 `endif
 
-//    ROM IF
-//O_ROM_AB,
-//I_ROM_DB,
-//O_ROM_OEn,
-//O_ROM_CSn,
-//O_ROM_WEn,
-
 //    INPORT SW IF
 I_PSW,
 
@@ -80,13 +73,6 @@ input	psRXD;
 output	psTXD,psCLK,psSEL;
 `endif
 
-//    ROM IF
-//output [18:0]O_ROM_AB;
-//input  [7:0]I_ROM_DB;
-//output O_ROM_OEn;
-//output O_ROM_CSn;
-//output O_ROM_WEn;
-
 //    INPORT SW IF
 input  [8:0]I_PSW;
 
@@ -95,9 +81,9 @@ output  O_SOUND_OUT_L;
 output  O_SOUND_OUT_R;
 
 //    VGA (VIDEO) IF
-output [4:0]O_VGA_R;
-output [4:0]O_VGA_G;
-output [4:0]O_VGA_B;
+output [3:0]O_VGA_R;
+output [3:0]O_VGA_G;
+output [3:0]O_VGA_B;
 output O_VGA_H_SYNCn;
 output O_VGA_V_SYNCn;
 
@@ -108,7 +94,7 @@ wire   W_CLK_12M,WB_CLK_12M;
 wire   W_CLK_6M,WB_CLK_6M;
 wire   W_STARS_CLK;
 
-dcm clockgen(
+mc_dcm clockgen(
 .CLKIN_IN(I_CLK_125M),
 .RST_IN(! W_RESETn),
 .CLKFX_OUT(I_CLK_18432M)
@@ -410,76 +396,23 @@ mc_inport MC_INPORT(
 //-----------------------------------------------------------------------------
 //------- ROM           -------------------------------------------------------
 reg    [18:0]ROM_A;
-wire   [10:0]W_OBJ_ROM_A;
-reg    [7:0]W_OBJ_ROM_A_D;
-reg    [7:0]W_OBJ_ROM_B_D;
 
 wire   [18:0]W_WAV_A0,W_WAV_A1,W_WAV_A2;
 reg    [7:0]W_WAV_D0,W_WAV_D1,W_WAV_D2;
 
-wire   [7:0]ROM_D; // = I_ROM_DB;
-//assign O_ROM_AB  = ROM_A;
-
-//assign O_ROM_OEn = 1'b0;
-//assign O_ROM_CSn = 1'b0;
-//assign O_ROM_WEn = 1'b1;
+wire   [7:0]ROM_D;
 
 galaxian_roms ROMS(
-.I_CLK_18432M(I_CLK_18432M),
-.I_CLK_12M(WB_CLK_12M),
-.I_ADDR(ROM_A),
+.I_ROM_CLK(W_CLK_12M),
+.I_ADDR({3'h0,W_A[15:0]}),
 .O_DATA(ROM_D)
 );
 
-
-reg    [1:0]clk_d;
-reg    [4:0]seq;
-always @(posedge I_CLK_18432M)
+always@(posedge W_CLK_12M)
 begin
-  // 24 phase generator
-   clk_d[0] <= W_H_CNT[0] & W_H_CNT[1] & W_H_CNT[2];
-   clk_d[1] <= clk_d[0];
-   seq <= (~clk_d[1] & clk_d[0]) ? 0 : seq+1;
-   case(seq)
-      0:begin
-        //sound
-        ROM_A <= W_WAV_A0;
-        W_CPU_ROM_DO <= ROM_D;
-        end
-      2:begin
-        //sound
-        ROM_A <= W_WAV_A1;
-        W_WAV_D0 <= ROM_D;
-        end
-      4:begin
-        //sound
-        ROM_A <= {3'h0,W_A[15:0]};
-        W_WAV_D1 <= ROM_D;
-        end
-      6:begin
-        //sound
-        ROM_A <= W_WAV_A2;
-        W_CPU_ROM_DO <= ROM_D;
-        end
-      8:W_WAV_D2 <= ROM_D; //sound
-     10:ROM_A <= {3'h0,W_A[15:0]};
-     12:W_CPU_ROM_DO <= ROM_D;
-     16:ROM_A <= {3'h0,W_A[15:0]};
-     18:begin
-        ROM_A <= {3'h0,4'h4,1'b0,W_OBJ_ROM_A};
-        W_CPU_ROM_DO <= ROM_D;
-        end
-     20:begin
-        ROM_A <= {3'h0,4'h5,1'b0,W_OBJ_ROM_A};
-        W_OBJ_ROM_A_D <= ROM_D;
-        end
-     22:begin
-        ROM_A <= {3'h0,W_A[15:0]};
-        W_OBJ_ROM_B_D <= ROM_D;
-        end
-     default:;
-   endcase
+	W_CPU_ROM_DO <= ROM_D;
 end
+
 //-----------------------------------------------------------------------------
 
 wire   W_V_BL2n;
@@ -530,10 +463,6 @@ mc_video MC_VID(
 .I_VID_RAM_RDn(W_VID_RAM_RDn),
 .I_VID_RAM_WRn(W_VID_RAM_WRn),
 
-.O_OBJ_ROM_A(W_OBJ_ROM_A),
-.I_OBJ_ROM_A_D(W_OBJ_ROM_A_D),
-.I_OBJ_ROM_B_D(W_OBJ_ROM_B_D),
-
 .O_C_BLnX(W_C_BLnX),
 .O_8HF(W_8HF),
 .O_256HnX(W_256HnX),
@@ -621,6 +550,10 @@ mc_vedio_mix MIX(
 
 );
 
+wire [2:0]W_VGA_R;
+wire [2:0]W_VGA_G;
+wire [1:0]W_VGA_B;
+
 `ifdef VGA_USE
 mc_vga_if  VGA(
 
@@ -633,9 +566,9 @@ mc_vga_if  VGA(
 .I_H_SYNC(W_H_SYNC),
 .I_V_SYNC(W_V_SYNC),
 // output
-.O_R(O_VGA_R),
-.O_G(O_VGA_G),
-.O_B(O_VGA_B),
+.O_R(W_VGA_R),
+.O_G(W_VGA_G),
+.O_B(W_VGA_B),
 .O_H_SYNCn(O_VGA_H_SYNCn),
 .O_V_SYNCn(O_VGA_V_SYNCn)
 
@@ -643,11 +576,11 @@ mc_vga_if  VGA(
 
 `else
 
-assign O_VGA_R[4:0] = W_R;
+assign W_VGA_R[2:0] = W_R;
 
-assign O_VGA_G[4:0] = W_G;
+assign W_VGA_G[2:0] = W_G;
 
-assign O_VGA_B[4:0] = W_B;
+assign W_VGA_B[1:0] = W_B;
 
 //assign O_VGA_H_SYNCn = W_H_SYNC | W_V_SYNC ;  //  AKIDUKI LCD USED
 assign O_VGA_H_SYNCn = ~W_H_SYNC ;
@@ -655,6 +588,12 @@ assign O_VGA_V_SYNCn = ~W_V_SYNC ;
 
 `endif
 
+assign O_VGA_R[3:0] = {W_VGA_R[0], W_VGA_R[1], W_VGA_R[2], 1'b0};
+
+assign O_VGA_G[3:0] = {W_VGA_G[0], W_VGA_G[1], W_VGA_G[2], 1'b0};
+
+assign O_VGA_B[3:0] = {W_VGA_B[0], W_VGA_B[1], 2'b0};
+
 wire   [7:0]W_SDAT_A;
 
 mc_sound_a MC_SOUND_A(