X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/fpga-games/blobdiff_plain/b884ab49c82cc350e3d74264cff4b9da0d664878..49502d5f0b235a30ac00eb83dfefe27ae18cd956:/galaxian/src/mc_video.v?ds=sidebyside

diff --git a/galaxian/src/mc_video.v b/galaxian/src/mc_video.v
index c93b557..c5af5e9 100644
--- a/galaxian/src/mc_video.v
+++ b/galaxian/src/mc_video.v
@@ -45,10 +45,6 @@ I_OBJ_RAM_WRn,
 I_VID_RAM_RDn,
 I_VID_RAM_WRn,
 
-O_OBJ_ROM_A,
-I_OBJ_ROM_A_D,
-I_OBJ_ROM_B_D,
-
 O_C_BLnX,
 O_8HF,
 O_256HnX,
@@ -80,10 +76,6 @@ input  I_OBJ_RAM_WRn;
 input  I_VID_RAM_RDn;
 input  I_VID_RAM_WRn;
 
-output [10:0]O_OBJ_ROM_A;
-input  [7:0]I_OBJ_ROM_A_D;
-input  [7:0]I_OBJ_ROM_B_D;
-
 output O_C_BLnX;
 output O_8HF;
 output O_256HnX;
@@ -127,7 +119,7 @@ end
 
 mc_ld_pls LD_PLS(
 
-.I_CLK_6M(~I_CLK_6M),
+.I_CLK_6M(I_CLK_6M),
 .I_H_CNT(I_H_CNT),
 .I_3D_DI(W_3D),
 
@@ -163,7 +155,7 @@ wire   [7:0]W_OBJ_RAM_A  = I_OBJ_RAM_RQn ? W_OBJ_RAM_AB: I_A[7:0] ;
 wire   [7:0]W_OBJ_RAM_DOA,W_OBJ_RAM_DOB;
 
 reg    [7:0]W_H_POSI;
-always@(posedge I_CLK_12M) W_H_POSI <= W_OBJ_RAM_DOB;
+always@(posedge I_CLK_6M) W_H_POSI <= W_OBJ_RAM_DOB;
 
 mc_obj_ram OBJ_RAM(
 
@@ -243,10 +235,27 @@ wire   [7:0]W_OBJ_ROM_AB = {W_OBJ_D[5:0],W_1M[3],W_OBJ_D[6]^I_H_CNT[3]};
 
 wire   [7:0]W_OBJ_ROM_A = I_H_CNT[8] ? W_OBJ_ROM_AB: W_VID_RAM_DOB;
 
-assign O_OBJ_ROM_A = {W_OBJ_ROM_A,W_1M[2:0]};
+wire   [10:0]W_O_OBJ_ROM_A = {W_OBJ_ROM_A,W_1M[2:0]};
+
+wire   [7:0]W_1K_D;
+wire   [7:0]W_1H_D;
+
+//1K VID-Rom
+GALAXIAN_1K K_ROM(
+.CLK(I_CLK_12M),
+.ADDR(W_O_OBJ_ROM_A),
+.DATA(W_1K_D),
+.ENA(1'b1)
+);
+
+//1H VID-Rom
+GALAXIAN_1H H_ROM(
+.CLK(I_CLK_12M),
+.ADDR(W_O_OBJ_ROM_A),
+.DATA(W_1H_D),
+.ENA(1'b1)
+);
 
-wire   [7:0]W_1K_D = I_OBJ_ROM_A_D;
-wire   [7:0]W_1H_D = I_OBJ_ROM_B_D;
 
 //---------------------------------------------------------------------------------
 wire   W_2L_Qa,W_2K_Qd;
@@ -330,16 +339,14 @@ begin
 end
 
 wire   [7:0]W_LRAM_A = W_45T_Q^{8{W_H_FLIP1X}};
-wire   W_LRAM_WE = ~I_CLK_6M;
 
 wire   [4:0]W_LRAM_DI;
 wire   [4:0]W_LRAM_DO;
 
 reg    [1:0]W_RV;
 reg    [2:0]W_RC;
-wire   W_1U_CLK = ~I_CLK_6M;
 
-always@(posedge W_1U_CLK)
+always@(negedge I_CLK_6M)
 begin
       W_RV <= W_LRAM_DO[1:0];    
       W_RC <= W_LRAM_DO[4:2];
@@ -370,7 +377,7 @@ mc_lram LRAM(
 
 .I_CLK(I_CLK_18M),
 .I_ADDR(W_LRAM_A),
-.I_WE(W_LRAM_WE),
+.I_WE(I_CLK_6M),
 .I_D(W_LRAM_DI),
 .O_Dn(W_LRAM_DO)